In this work, we present two new oscillator structures based on using two amplifiers surrounded by four impedances Z1−4. The structures are generic in the sense that they are not based on any specific active device and hence can be realized in numerous different ways. We focus our attention on deriving all possible canonical second-order RC and LC oscillators that can be obtained from each of the proposed structures. In some of the found circuits, the oscillation frequency can be independently tuned using one of the two amplifiers while the start-up condition is set by the other amplifier. Spice circuit simulations and experimental results are provided to validate the theory.

In this work, we show that a pinched-loop can be observed in the voltage-current plane when a series R-L circuit is current excited. Specifically, the resistance (R) in this circuit is variable and is voltage-controlled by the voltage developed across the inductor due to the exciting current. In this context, we confirm our previous results that the pinched-loop is not a characteristic of memrsitors or memrsitive systems and that it can be observed in many other nonlinear systems. Numerical simulations, circuit simulations and experimental results validate the theory.

A CMOS wideband voltage-mode fully differential all-pass filter (APF) is discussed. The APF circuit consists of three transistors, two inductors, two capacitors, and four resistors. The proposed APF employs the generic two-transistor common-source amplifier structure. Design procedures along with parasitic analysis are presented for wideband applications. The proposed APF is designed and fabricated in a 65-nm CMOS process. The operation of the proposed APF is validated by experimental and post-layout simulation results. The filter experimentally demonstrates a group delay (GD) of 59 ps at 26 GHz and it has less than 10% delay variation across a wide bandwidth of 24-29 GHz. The implemented design occupies an area of 0.09 mm2and consumes 5.1 mA from 1 V supply voltage. The noise and linearity performances of the proposed APF are validated by post-layout simulation results. The filter has a noise figure of 8.6-8.9 dB across 24-29 GHz and it achieves an input- referred IP3 of -1.14 dBm.

In this article, a synthesis methodology for analog circuit design is presented. This methodology utilizes symbolic math tools to systematically and exhaustively search for candidate analog circuits avoiding tedious manual work. The two-port network matrix representation of active devices, such as MOS transistors, paves the way for efficiently using advanced symbolic math toolboxes (e.g., in MAPLE or MATLAB) to automate the generation of new analog circuits and further investigate the effects of nonidealities and parasitics. Using this synthesis methodology new amplifiers, filters, and oscillators can be obtained starting from a predefined structure. This article aims to motivate and provide an overview of the current status of research in this area. In addition, two detailed design examples of a family of differential filters and a family of differential oscillators along with their simulations and measurement results are provided to illustrate and verify the synthesis methodology.

In this paper, the generation of differential-input differential-output second-order active filters based on a common-source differential amplifier is systematically conducted using two-port network modeling techniques which enable exploiting the power of symbolic math CAD tools. Starting from a generic two-transistor differential-pair structure, and the maximum possible number of surrounding impedances, all possible filters are derived and classified. In particular, 35 transfer functions and a total of 876 filters are found to be possible. Due to employing a $2\times 2$ transmission matrix representation of each transistor, flexibility in examining parasitic effects on the derived transfer functions is achieved and can be easily automated within the design framework. Selected filters are constructed and experimentally verified using discrete transistors. The operation of some filters is also verified with simulations using a 65-nm CMOS process.

In this paper, the generation of fully differential 2ndorder voltage-mode allpass filters is systematically studied and modeled using two-port network techniques. The proposed filters are based only on the generic two transistor common-drain differential pair and a series of surrounding RLC impedances. Five designs of possible allpass filters based on various choices of the surrounding impedances are also presented. Selected designs were verified with experimental results using discrete MOS transistors as proof of concept. One of the proposed filters was simulated in 65-nm CMOS and showed 46GHz delay-bandwidth while the delay can be electronically tuned via the bias current and independent from the pole frequency.

The increasing interest in bio-impedance analysis in various fields has increased the demand for portable and low-cost impedance analyzers that can be used in the field. Simplifying the hardware is important to maintain low-cost and portability, but this is not an easy task due to the need for accurate phase and magnitude measurements. In this paper, a magnitude only hardware design is proposed and tested. The need to measure the phase is replaced by using a modified Kramers-Kronig transform to extract the phase from the magnitude information. Testing using on-shelf components, and comparisons using apple bio-impedance measurements from a professional impedance analyzer are also reported.

An analog all-pass filter based transfer function synthesis method is proposed for realizing multifunctional microwave active circuits. An analog realization is obtained by replacing unit sample delays in an existing digital prototype with a second-order all-pass analog filter. A novel space time array processor (STAP) and a frequency and bandwidth agile multi-band filter have been simulated using the proposed transfer function synthesis method using measured S- parameters of a fabricated 130 nm second-order CMOS all- pass filter. Simulated array patterns of the STAP beamformer show improved side-lobe performance for better interference suppression and noise rejection. The tunability of the multi-band analog filter, in terms of the center frequency and the quality factor, is verified up to 8 GHz, which has potential applications in analog microwave front-ends.

Impedance spectroscopy is a powerful tool to study the frequency behavior of supercapacitors, but it comes with pricy hardware and postprocessing routines. Here we present a non-impedance method to extract the fractional-order model parameters (Rs, Cα, α) of a supercapacitor-assumed to be equivalent to a series association of a resistance with a constant phase element-using the magnitude response of a measurement circuit consisting of a large bandwidth operational amplifier with negative feedback. The theory behind the measurement circuit, along with the extraction method of the model parameters, and validation within 1% error using simulated and experimental results from a commercial supercapacitor are presented and discussed.

The Cole impedance model is widely used in applications involving the electrical impedance of biological tissues. Typically requiring post-processing to determine its four parameters from electrical impedance measurements. Here, a nonlinear least squares optimization routine is applied to extract the Cole impedance parameters from collected magnitude responses (not requiring direct impedance measurements). The aim is to quantify the impact of the measured frequency range, number of collected datapoints, and level of noise in the magnitude-only measurements on the accuracy of the extracted parameters. Further investigating the impact the optimization settings have on the accuracy and time required to extract the parameters. The aim is to understand these factors' effects towards the implementation of embedded systems utilizing this method to extract the impedance parameters.

In this paper we propose using a non-linear least squares fitting process to estimate the impedance parameters of a fractional order model of supercapacitors from their collected step response datasets, without requiring direct measurement of the impedance or frequency response. Experimentally estimated parameters from 1 F supercapacitors verify the proposed time domain method showing less than 2% relative error between the simulated response (using the extracted fractional parameters) and the experimental step response, over the entire dataset.

In this paper we propose using a method of non-linear least squares to extract the Cole-Cole impedance parameters (Ro, R∞, α, τ) from collected frequency response datasets. We show how this method reduces the error of the extracted parameters when compared to direct extraction methods whose accuracy are limited by the measured low and high frequency gains. Parameters extracted using the non-linear least squares show up to 4 orders of magnitude lower relative error from ideal simulated datasets compared to direct methods. Experimentally extracted parameters from fruit tissue frequency responses verify the accuracy of the proposed non-linear least squares method over the direct extraction method.

A new digitally-controlled exponential variable gain amplifier is presented in this paper. This circuit is based on the proposed novel method of expanding the dynamic range over which a traditional approximate function estimates the ideal exponential function. The technique is unique in a way that it culminates in a true exponential amplifier over an improved input dynamic range. Tuning in this circuit has been achieved using a single digitally switched variable resistor. Finally, the circuit has been implemented in a TSMC 0.18 μm CMOS technology and displays a gain from about - 21 dB to 36 dB in steps of 3.89 dB with a linear error in [-0.66 dB, 0.45 dB].

In this paper we propose a fractional lowpass transfer function of the order (n + α) where n is an integer and 0α. A 1storder lowpass filter with fractional steps from 0.1 to 0.9, that is of order 1.1 to 1.9 is given as an example with its characteristics compared to 1stand 2ndorder Butterworth filters. PSPICE simulations and experimental results of a prototype filter verify the operation of the fractional step filter.

A time-based approach to SerDes data transfer is described. As proof of concept, 2-bit 800 Mbps and 3-bit 1.2 Gbps time-based serial links have been designed and implemented using an Altera transceiver signal integrity development FPGA kit. The eye diagram of both the transmitted signal and the signal at the end of a 40-inch FR4 trace have been measured and compared for both links. The transmitted code has been successfully recovered at the receiver side.

In this paper the design of a 5 GHz wide band matched low noise amplifier (LNA) is presented. The LNA uses a conventional cascode architecture and was implemented in IBM SiGe5AM technology. Powered by a 1.8-V supply the LNA features 11.5 dB of gain and a 1.2 dBm noise figure. The LNA has a bandwidth of 3 GHz which makes is suitable for wide band applications. The LNA draws only 8mA current and is stable over a wide frequency range. Input and output return losses of -10dB and -13dB have been achieved.

In this paper we present an innovative approach to VLSI implementation of Q tuning of analog lowpass filters. The proposed scheme uses the LMS algorithm to adaptively compensate changes in input amplitude and frequency. A tunable OTA is designed to implement the automatic control loop in the integrated circuit. The tuning system was implemented in CMOS 0.18 µ m technology in a master-slave configuration.

A novel variation of the cross-coupled operational transconductance cell is presented in this paper. The conventional cross-coupled cell has a differential input linearity range that is dependent on the control voltage. The proposed design removes that restriction while allowing the same tunability using the control voltage. Its input may also be single or fully differential unlike the conventional cross-coupled cell, which requires a fully differential input. Results were confirmed using HSPICE simulations.

A new CMOS realization of an operational transconductance amplifier is presented. It is based on the cross-coupled configuration and is biased by the common-mode voltage. The circuit has only two transistors between the supply line and ground which makes it suitable for low-voltage applications. Simulation results show that the circuit is highly linear and tunable over a wide range bias voltage. The circuit is used to realize 2/sup nd/ generation current conveyor (CCII) and differential current conveyor (DCC) that have excellent performance.

This paper presents general first and second order switched-current building blocks. The circuits can be easily implemented in standard CMOS technology without the need of a capacitance layer. The circuits can be used to realize almost any transfer function with high accuracy. A sixth-order cascade Chebyshev band-pass filter was realized using the proposed building blocks and simulated using HSPICE. The simulation results were very favorable.>