This paper proposes a fully-integrated Gate Driver with on-chip GaN power transistors for the application of underwater wireless charging circuit. Because of the absense of PMOS transistor in the GaN process, the novel Comparator, Voltage Reference circuit, Dead-time Generator, Short-pulse Generator, and output Buffer implemented using D-HEMT and E-HEMT are proposed in this work to improve the performance and the efficiency. The novel Comparator is used for generating the PWM control signal for adjusting the output power. The proposed Dead-time and Short-pulse Generator are used to prevent the high-side and low-side transistors conducting simultaneously. The novel Voltage Reference circuit is to provide a stable DC voltage for the Voltage Regulator at all PVT corners. The novel output Buffer could drive the integrated GaN power transistors efficiently by using the E-HEMT as the pull-high element. The proposed design is implemented with TSMC 0.5 μm GaN process. The chip area is 3217.55 × 3709.25 μm2. The simulation results present the proposed design with an output slew rate of 76.2 V/ns, an efficiency of 98.9%, and an output power of 62.5 W.

This paper proposes a low-power 3.2-GHz 0.3/0.5 V I/O Buffer. By using the proposed Output Buffer with parallel PMOS and NMOS transistors as the pull-up and pull-down networks, the 0.3 V low-voltage signal could be transmitted without the extra NLC (Negative Level Converter) as the gate driver. At the Input Buffer, the source terminal of the NMOS transistor is used as the input terminal, such that the 0.3 V input signal could be received without using low threshold-voltage transistors. Moreover, the Low-Power PVT compensation circuit without various threshold-voltage transistors is proposed to compensate the delay time variation for all PVT corners. The proposed design is implemented with TSMC 16-nm FinFET process. The core area is 38.77 × 67.49 μm2. With the PVT compensation, the eye height ratio becomes 93% and 94% for VDDIO at 0.3 V and 0.5 V, respectively. The eye width is improved to 0.85 UI. The delay time variation is reduced by 45.03% in the worst case. The power consumption is 5.338 μW/MHz.

This paper presents a novel 6-Gbps variation insensitive input/output (I/O) buffer designed for DDR4 and DDR5 SDRAM data transfer in a 16-nm FinFET CMOS process. Utilizing genetic algorithm (GA) to model process, voltage, and temperature (PVT) variations, the study reveals insights into temperature and voltage effects on FinFET-based, nanoscale buffer characteristics, leading to the removal of the temperature detector circuit to save power and area. Voltage variations, however, significantly impact slew rate, prompting the introduction of a Voltage Detector circuit using ultra-low threshold voltage (ULVT) transistors. Innovative Voltage Level Converter, Pre-Driver, and Digital Logic Control circuits enhance slew rate and throughput while stabilizing the output signal quality. This results in reliable operation at 6.0 Gbps with improved slew rate (17.7%/39.75% for VDDIO =0.8/1.2 V) and duty cycle performance (50.5%/51.4% for VDDIO =0.8/1.2 V) due to PV auto-adjustment; the first in the world. The proposed design effectively addresses the stringent slew rate and data rate requirements of DDR4 and DDR5 SDRAMs, offering advancements in speed, reliability, and efficiency amidst PV variations.

This paper presents a SIDO buck-buck converter for separate positive and negative voltage. To provide the gate driving voltage for the dual-mode low voltage output buffer, 0.5 V and 0.3 V are obtained for the first output, -0.4 V and -0.6 V are generated for the second output. With the new structure of the proposed buck-buck converter, only 7 major devices are utilized including 1 inductor, 2 capacitors and 4 switches. The proposed design is implemented with a typical 40 nm CMOS process. The core area is$\mathbf{484}.\mathbf{72}\times \mathbf{556}.\mathbf{875}\ \boldsymbol{\mu}\mathbf{m}^{2}$. The peak efficiency is 91.282% for the dual output at 0.5 V and -0.4 V, respectively. The cross regulation of the first output is 0.026 mV/mA and 0.022 mV/mA for the modes of 0.5 V and 0.3 V, respectively.

This paper presents a low power 3.2 Gbps output driver. By using the Negative Level Converter (NLC) to provide the negative driving voltage, the output driver could be operated at low voltage of 0.5 V and 0.3 V. To compensate the delay time variation caused by the severe variation of process, voltage, and temperature (PVT), the low power PVT compensation circuit with stacked subthreshold MOS transistors is proposed. Unlike traditional PVT compensators for output driver, the clock and the DFF are not required such that the power consumption is reduced. The proposed design is implemented with a typical 40 nm CMOS process. The core area is$56.35\times 72.93\ \mu\mathrm{m}^{2}$. With the PVT compensation, the eye height ratio is 98.7% and the eye width is 0.947 UI for VDDQ at 0.3 V. The delay time variation is improved by 28.7% and 28.8% for VDDQ of 0.3 V and 0.5 V, respectively. The power consumption is 20.875$\mu \mathrm{W}/\text{MHz}$.

This paper presents a high efficiency buck converter with wide load current range. To improve the efficiency in wide load current range, the dual-mode of PWM and PSM is utilized. The proposed design is implemented with a typical 0.35 μm CMOS process. The peak efficiency is simulated to be 96.76% at load current of 1000 mA. Moreover, the efficiency is higher than 94.80% at the wide load current range from 10 mA to 1000 mA. Besides, the proposed design is switched smoothly between PWM and PSM by effective and reliable control logic circuit.

This paper proposes a 40-nm CMOS 2×VDD buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors, five process corners for both nMOS and pMOS could be detected. Thus, the SR deviations will be significantly reduced by controlling the switches of the output stage accordingly. Besides, leakage reduction circuit will shut down current paths to reduce dynamic leakage after signal transitions are completed. This buffer design is implemented using the typical 40-nm CMOS process, where the active area is 0.052 × 0.213 mm2. The measured worst case of SR variation improvement is 20.8% and 54.9% when VDDIO is 0.9 and 1.8 V, respectively. The peak dynamic leakage is reduced to 41.0% and 37.5% at 0.9 and 1.8 V, respectively.

Various implantable microstimulators have been proposed for clinical applications in recent years. Most of the no-battery implanted devices can be powered by a transcutaneous magnetic coupling, which basically utilizes an external transmitter coil to power and communicate with the implanted device. Small chip area and low power consumption are the keys of the implanted device. Therefore, we propose a C-less (no capacitor) area-saving ASK demodulator in this work to get rid of those large discrete capacitors required for low-frequency ASK demodulation. Additionally, a power regulator supplying a stable VDD/spl I.bar/OUT is also built in to resolve the unstable supply voltage problem resulted from the inductive link. Besides, a multiparameter control protocol which has an area advantage over microcontroller-based solutions is also proposed for various pain treatments of muscles and stimulating applications.