As technology advances, digital circuits are reaping the benefits more than its analog counterpart. Time-to-Digital converters (TDC) are aiding the transition of some traditionally analog circuits into the digital domain. In this paper, a 14-bits fully synthesizable stochastic-based branching TDC is proposed. As compared to prior work, it has its own oscillation source on-chip. Moreover, it has a coarse-fine architecture with a smooth coarse-fine interface that allows it to extend its range easily without incurring large overhead costs. It was synthesized in a standard 65nm/1.2V CMOS technology using a VDD of 0.8 V. It is expected to achieve a resolution of 850fs. Simulation results shows a DNL & INL of 0.27 & 2.94LSB respectively, with a FoM of 136/J/conv. step. At a sampling rate of 125MS/s, it consumes 70.8mWof power.

A W-band ultra-high data-rate (56Gb/s) wideband (68-102GHz) 65nm bulk CMOS wireless transceiver is presented. Frequency interleaving by two up-converted IF data signals using 68 and 102GHz LO to W-band is applied to achieve wideband and a world-record 56Gb/s wireless communications on CMOS. 16QAM modulation is used for 6.5GHz (26Gb/s) low-band and 7.5GHz (30Gb/s) high-band data. Transmitter/receiver (TX/RX) consumes 260/300mW from 1V DC supply.

This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm2. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL up-to-date.

This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed frequency synthesizer is fabricated in 65nm CMOS process and it is capable of working at frequencies ranging from 4.3GHz to 4.9GHz. The measured close-in phase noise is −113dBc/Hz at an offset of 200kHz from the carrier with 3.3mW power consumption, which results in a FoM of −246dB.

This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of -224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N injection-locked PLL up-to-date.

This paper presents a time-to-digital converter (TDC) using delta-sigma (ΔΣ) architecture which utilizes a charge pump as the time to voltage converter and a low bit SAR ADC as the quantizer. By never resetting the capacitor connected to the charge pump, a simple integrator is realized and first order noise shaping is achieved. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 1 MHz bandwidth, simulation shows that this TDC achieves 74.9 dB SNDR and 269 fsrms integrated noise for ±1.5 ns input range. The proposed TDC consumes 0.9 mW power from 1 V power supply that translates to FoM of 99 fJ/conv.

This paper proposes a tail-current modulated VCO with adaptive-bias scheme. The proposed adaptive-bias scheme ensures robust startup conditions for the tail-feedback VCO. A tail-feedback VCO using the proposed scheme is implemented in a 0.18-μm CMOS process. The measured phase noise is -119.3dBc/Hz at 1MHz offset with a power dissipation of 6.8mW at 4.6GHz.

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.

This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm2. It achieves the best performance-area trade-off.

This paper discusses the ultralow-voltage (ULV) design strategy for high-speed flash analog-to-digital converters (ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. In this paper, a new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and conversion speed. As a prototype, a 0.5 V, 420-MS/s, and 7-bit, flash ADC is developed using a 90-nm CMOS technology to demonstrate the validity of ULV operation. To overcome the challenges associated with a reduced supply voltage, a double-tail latched comparator with a variable capacitance calibration technique using metal-oxide-metal capacitors is implemented. An all-digital time-domain delay interpolation technique further enhances the resolution with very little additional power consumption. Using two-way time-interleaving, the prototype ADC achieves an effective number of bits (ENOB) of 5.5 bits while operating at 420 MS/s consuming a total power of 4.1 mW. The lowest measured FoM is the 195 fJ/conv.-step during single-channel operation at 210 MS/s, which results in an extremely low FD product of 0.93 pJ × ns/conv.-step.

This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2resulting in the best performance-area trade-off system presented up-to-date.

A swing-enhanced current-reuse class-C VCO which can theoretically achieve same phase noise figure-of-merit (FoM) as other class-C VCOs at the lowest power consumption is presented. A swing enhancement in class-C operation and an oscillation robustness are achieved through dynamic bias control circuits for both NMOS and PMOS transistors. The proposed VCO has been fabricated in 180nm CMOS process while oscillating at 4.6 GHz. The measured phase noise is -119 dBc/Hz at 1 MHz offset while consuming 1.6 mA from 1.5 V supply. An FoM of -189 dBc/Hz is achieved.

This paper presents an area-efficient frequency synthesizer with a quadrature phase output using a fractional-N injection-locking technique for software-defined radios. A background calibration scheme is proposed to compensate for the PVT variations. Implemented in a 65nm CMOS process, this work demonstrates 10 MHz to 6.6 GHz continuous quadrature frequency coverage, while only occupies a small area of 0.38 mm2and consumes 16-26 mW depending on output frequency, from a 1.2 V power supply. The normalized phase noise achieves -135.3 dBc/Hz at 3 MHz offset, and -95.1 dBc/Hz in-band phase noise at 10 kHz offset, from a 1.7 GHz carrier frequency.

This paper presents a 60-GHz direct-conversion transceiver in 65 nm CMOS technology. By the proposed gain peaking technique, this transceiver realizes good gain flatness and is capable of more than 7 Gbps in 16QAM wireless communication for all channels of IEEE802.11ad standard within EVM of around -23 dB. The transceiver consumes 319mWin transmitting and 223mW in receiving, including the PLL consumption.

A 58.1-to-65.0 GHz frequency synthesizer using sub-harmonic injection-locking technique is presented. The synthesizer can generate all 60GHz channels defined by IEEE 802.15.3c, wirelessHD, IEEE 802.11ad, WiGig, and ECMA-387. A frequency calibration scheme is proposed to monitor frequency shift resulting from environmental variations. Implemented in a 65nm CMOS process, the synthesizer achieves a typical phase noise of -117 dBc/Hz @10MHz offset from a carrier frequency of 61.56 GHz.

This paper presents a feedback class-C VCO with PVT-robustness and enhanced oscillation swing. The proposed VCO starts oscillation as a differential LC-VCO for robust startup, and automatically adapts to an amplitude-enhanced class-C VCO in steady-state for lower phase noise. The proposed VCO is implemented in a 0.18μm CMOS process. The measured phase noise at room temperature is -125 dBc/Hz @ 1MHz offset with a power dissipation of 3.4-mW, from a carrier frequency of 4.84-GHz. The figure-of-merit is -193 dBc/Hz.

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The 65 nm CMOS transceiver realizes the IEEE802.15.3c full-rate wireless communication for every 16QAM/8PSK/QPSK/BPSK mode. The maximum data rates with an antenna built in a package are 8 Gbps in QPSK mode and 11 Gbps in 16QAM mode within a BER of-3. The transceiver consumes 186 mW while transmitting, and 106 mW while receiving. The PLL also consumes 66 mW.

This paper proposes Progressive Mixing Injection Locked Frequency Divider (PMILFD) technique that enhances the locking range for higher division ratios. As this technique uses lower and much stronger harmonics in the mixing process, it results in a stronger injection effect and a much wider locking range. Two 20GHz PMILFDs were designed based on this approach to divide by 4 and 8 using a 65nm CMOS process. The former achieves a 7.9GHz(31.4%) locking range and the later achieves a 3.4GHz(15.5%) while consuming 3.9mW and 7.1mW, respectively.

This paper proposes a 0.5-V LC-VCO with a frequency extension circuit to replace ring oscillators for ultra-low-voltage sub-1ps-jitter clock generation. Significant performances, in terms of 0.6-ps jitter, 50MHz-to-6.4GHz frequency tuning range with 2 bands and sub-1mW PDC, indicates the successful replacement of ring VCO for the future 0.5-V LSIs and power aware LSIs.

This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results show a phase noise of -96dBc/Hz at 60GHz while consuming 77.5mW from a 1.2V supply.

This paper presents a high-speed, low-power and wide signal swing differential dynamic amplifier using a common-mode voltage detection technique. The proposed dynamic amplifier achieves a 15.5 dB gain with less than 1 dB drop over a signal swing of 1.3 Vppat an operating frequency of 1.5 GHz with a VDDof 1.2 V in 90 nm CMOS. The power consumption of the proposed circuit can be reduced linearly with operating frequency lowering.

A tunable power amplifier (PA) from 2.1 GHz to 6.0 GHz is presented for multi-standard radios. The proposed multi-band PA can tune the output impedance to 50 ¿ over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 ¿m CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22of smaller than -8 dB, power gain of larger than 12 dB, output 1-dB compression point of larger than 15 dBm.

This paper presents a 60 GHz direct-conversion transmitter in 65 nm CMOS technology. The power amplifier consists of 4-stage transistors. The circuit model of de-coupling capacitor is built as a transmission line to consider the physical length. In the measurement results, the conversion gain is above 9.6dB at 58–65GHz band, and the 1 dB compression point is 1.6 dBm with 60 GHz LO frequency and 1 dB LO power.

This paper proposes a novel direct sampling mixer (DSM) using Switched Capacitor Filter (SCF) for multi-band receivers. The proposed DSM has a higher gain, more flexibility and lower flicker noise than that of conventional circuits. The mixer for Digital Terrestrial Television (ISDB-T) 1-segment was fabricated in a 0.18 μm CMOS process, and measured results are presented for a sampling frequency of 800 MHz. The experimental results exhibit 430 kHz signal bandwith with 27.3 dB attenuation of adjacent interferer assuming at 3 MHz offset.

This paper presents the design and preliminary results of a full differential sample-and-hold circuit based on the “flipped voltage follower” (FVF) cell. The heart of this circuit is a fully differential low-voltage OTA based on FVF technique. The use of the FVF reduces the supply power requirements in the OTA. To overcome input sampling switches limitation imposed by the low supply voltage we make use of a low-voltage low stress and reliable clock signal doubler. It is evidenced how different versions of theses cells, coined as ”flipped voltage follower (FVF)” and voltage doubler have been used in the past for many applications Preliminary simulation results in a 0.18 μm digital CMOS process show that a resolution greater than 8 bits can be obtained with a 1.0 V supply voltage using a 1 MHz clock signal. Further investigations on the performance limit of the proposed method as well as reliability concerns will be performed on the experimental test chip.

This paper proposes a multiple-divide technique using by-2, by-3, and by-4 frequency dividers to realize a lower phase-noise LC-VCO, and explores the design space of low-phase-noise VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than −191 dBc/Hz of FoM, can be extended from 6–12 GHz to 1.5–12 GHz.

A method of direct input reference feedforward compensation is proposed and discussed for all digital phase locked loop based synthesizers. The practical issues in implementing the system are addressed, and analysis of the feedforward estimation error on the system is performed. A sample model was created and simulated. Simulation shows the effect of the feedforward estimation error on the system's settling speed. The system was shown to be able to reduce the settling time to one eighth of the minimum achievable settling speed of a system without feedforward compensation.

SoC (System on a Chip) is a powerful solution to increase system performance and to reduce system cost, in particular for digital consumer products. SoCs for DVD, DTV, DSC, DVC, and cellular phone are current main LSI products for the digital consumer market. However current SoC has tough issues. A large system will continue to need Soc technology with scaled device; however the number of SoC design will decrease with time. Increase of development time and cost, insufficient performance, insufficient size of market for each application will make the choice of SoC difficult. Embedded circuit of which area is not scalable with technology scaling will make a serious issue in SoC. Cost of this circuit will increase with technology scaling according to A. Matsuzawa (2002). As a result, large analog circuit and some kind of memory will not able to be embedded in future SoC. SiP (System In a Package) looks strong alternative to address this issue. Different devices, such as different technology nodes, different functions, different materials, and some high performance passive devices can be integrated easily in a package. Conventionally some chips do not need to be developed, even if the system configuration and specification are changed. This reduces the development time and cost. Of course, SiP technology has some issues, such as decrease of signal transfer speed, insufficient number of connection, poor design tools, testing and known good die, and reliability. However today is too early to judge this technology is hopeless. We need more time to develop and mature the technology.

In this paper, motion vector (MV) estimation methods with high-speed intermediate pictures for low-power video compression are proposed. The intermediate pictures are obtained by a special type of CMOS image sensor. An adaptive iterative-search block matching is proposed to obtain precise MVs of video-rate pictures from high-speed intermediate pictures with the reduced computational complexity. The sensor captures high-speed intermediate pictures without destructing signal charge and video-rate pictures with full signal accumulation time. The proposed active pixel sensor using bidirectional multiple charge transfer is useful for the nondestructive intermediate imaging with a reduced fixed pattern noise. The image sensor chip has been implemented by using 0.35-/spl mu/m CMOS technology. It operates with 3.3 V and captures 480 frames/s high-speed nondestructive intermediate pictures and 30 frame/s fully accumulated video-rate pictures. The proposed adaptive iterative-search block matching has a comparable precision to a full search block matching with reduction of computational complexity by a factor of about 1/13, on average. It also reduces the data-loading rate from the memory by a factor of about 1/4.

This paper describes CMOS image sensors integrating video compression circuits. The on-sensor compression is particularly useful for the low-power design of moving picture compression hardware, which is demanded especially in the mobile computing and telephony. Recent progress of the CMOS image sensor technology allows us to realise the integration of high-performance image sensor and computational functions on a chip. An example of the CMOS image sensor with compression is described. Prospects of the CMOS image sensors with moving picture compression are discussed.

A CMOS smart image sensor LSI with video compression is presented. The proposed on-sensor compression scheme using an analog 2-D DCT processor is particularly useful to achieve low-power one-chip digital camera. A prototype image sensor LSI has been developed using 0.35 /spl mu/m double polysilicon, triple metal CMOS technology. Image coding using the implemented LSI has been demonstrated.

The goals of the studies of the MNABST-1 IC device were as follows: study the technical and economic feasibility of adding P1149.4 structures into mixed-signal devices; elicit design considerations at the silicon level and for silicon design software; study the interoperability of P1149.4 with 1149.1 interconnection test algorithms; study the efficacy of discrete component and network value measurements; establish limits on analog value measurements; and predict the capabilities of P1149.4 in the future. The results shows that we can emulate the capabilities of in-circuit test for most types of components currently tested this way. This will preserve the advantages of this well-known technology into the future when direct nodal access will no longer be the rule, but rather the exception.

This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses a boosted and offset-grounded data storage (BOGS) scheme. The key target of BOGS is to minimize the charge amount supplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (V/sub 0/=V/sub GS/-V/sub T/) up to 0.8 V necessary to achieve 100 MHz operation even at 0.5 V single power supply. Thus, the key low-power strategy of BOGS is "putting the right (higher efficiency) boosted power-supply from charge pump circuit into the right position (less power consumed transistor) in a SRAM cell." This paper is focused on why BOGS can realize a greater savings of the charge amount supplied from the boosted power-line and can reduce the power dissipation to /spl les/1/30.4 and /spl les/1/3.9 compared to the previously reported negative source-line drive (NSD) scheme and negative word-line drive (NWD) scheme, respectively, while achieving a 0.5 V/100 MHz operation.

This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses an over-V/sub CC/ grounded data storage (OVGS) scheme. The key target of OVGS is to minimize the charge amount supplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (V/sub 0/=V/sub GS/-V/sub T/) up to 0.8 V necessary to achieve 100 MHz-operation even at 0.5 V single power-supply. Thus, the key low-power strategy of OVGS is "putting the right (higher efficiency) boosted power-supply from the charge pump circuit into the right position in the SRAM cell". This paper focuses on why OVGS can realize a greater saving of the charge amount supplied from the boosted power-line and can reduce the power dissipation to /spl les/1/30.4 and /spl les/1/3.9 compared to the previously reported negative source drive (NSD) scheme (Mizuno et al., 1995) and negative word-line drive (NWD) scheme (Itoh et al., 1996), respectively, while achieving a 0.5 V/100 MHz-operation.