With the scaling down of the transistor technology, intrinsic gains of the devices are continuously dropping. Meanwhile, high-gain operational transconductance amplifiers (OTAs) using technologies with reduced feature sizes are required in various applications. This article presents a 55-nm-fabricated three-stage OTA with a single cascode Miller capacitor for driving large capacitive loads. To achieve a high dc gain, a gain enhancement (GE) circuit is used in the first stage to boost the overall voltage gain to above 100 dB. To obtain a stable frequency response, a cascode Miller compensation scheme together with the GE circuits are used to push the nondominant complex pole to higher frequency and adjust the$Q$-factor. The proposed three-stage OTA is implemented in a 55-nm low-power (LP) CMOS process and occupies an area of 0.005 mm2. A current consumption of$157 \mu \text{A}$can be measured with a supply voltage of 1.2 V. The measured results show that this three-stage OTA can achieve stable frequency and transient step responses when driving 2.5-to-30-nF capacitive loads. With a 15-nF capacitive load, a gain bandwidth (GBW) of 0.82 MHz, a phase margin (PM) of 53°, an average slew rate of 0.13 V/$\mu \text{s}$, and an average 1% settling time of$2.62 \mu \text{s}$can be achieved.

The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not.

This article presents a new analog circuit optimization system for automated sizing of analog integrated circuits. It consists of a genetic algorithm (GA)-based global optimization engine and an artificial neural network (ANN)-based local optimization engine. The key new idea is to use parallel computation to train ANN models for design space neighborhoods thus the local minimum search (LMS) can have a much faster search speed. For the GA-based global optimization, circuit performances are calculated by parallel SPICE simulations. For the LMS, circuit performance data are derived from ANN model predictions instead of SPICE simulations. Since the most time for an ANN-based LMS is spent on SPICE calls which can be run in parallel, the LMS process can also exploit the multiple core configuration of a modern computational server in addition to the GA global search. The fully parallelized optimization system is deployed to design a two-stage rail-to-rail operational amplifier and a fifth-order active-RC Chebyshev complex band-pass filter. The experimental results show that the proposed method provides about four times speed enhancement and comparable results compared with traditional approaches employing the same parallel global optimization but sequential SPICE calls during LMS.