Glass interposers have become a compelling option for 2.5-D heterogeneous integration compared to silicon. It allows 3-D stacking configuration between the embedded dies and the conventional flip-chip dies mounted directly on top at low cost. Furthermore, the interconnect pitch and through-glass-via (TGV) diameter in glass are becoming comparable to their counterparts in silicon. In this study, we investigate the power, performance, area (PPA), signal integrity (SI) and power integrity (PI) advantages of 3-D stacking afforded by glass interposers over silicon interposers. Our research employs a chiplet/package co-design approach, progressing from an register-transfer-level description of RISC-V chiplets to final graphic data system (GDS) layouts, utilizing TSMC 28 nm for chiplets and Georgia Tech’s 3-D glass packaging for the interposer. Compared to silicon, glass interposers offer a$2.6\times $reduction in area, a$21\times $reduction in wire length, a 17.72% reduction in full-chip power consumption, a 64.7% increase in SI and a$10\times $improvement in PI, with a 35% increase in thermal. Furthermore, we provide a detailed comparative analysis with 3-D Silicon technologies. It not only highlights the competitive advantages of glass interposers, but also provides critical insights into each design’s potential limitations and optimization opportunities.

Modern high performance integrated systems demand high-power (>1 kW) to be delivered at high current density (>2 A/mm2) from PCB to points-of-load (POLs) on-chip. Efficient delivery of high-quality power from PCB to POLs is a primary concern in modern high-power high-density integrated systems. With traditional power delivery approaches, high voltage is converted to high current on PCB, yielding prohibitively high power loss in horizontal packaging interconnect components. One approach to reduce this loss is with vertical power delivery (VPD), i.e., to deliver low current at high voltage horizontally and convert it to high current low voltage close to POLs. Voltage regulators (VRs) integrated within small footprint near POLs, however, exhibit high switching and inductor losses. As a result, state-of-the-art VPD systems still exhibit high IR voltage drops, power efficiency of less than 70%, and high thermal dissipation. Thus, the design of compact power efficient VRs is a primary concern with VPD approach. To enhance the overall performance of the PCB-to-POL power delivery system, distributed VPD is considered and architecture-specific design of VRs is investigated in this paper. The design methodology for determining optimal number and placement of VRs for a given power delivery architecture is also proposed. The approach has been demonstrated with on-interposer 12V/1V power converters, comprising Gallium Nitride (GaN) power devices and state-ofthe-art inductors and capacitors, yielding 85% power efficiency with 1-kA load at 2 A/mm2.

In this article, we present three commercial-grade 3-D IC designs based on state-of-the-art design technologies, specifically microbumping (3-D die stacking), hybrid bonding (wafer-on-wafer bonding), and monolithic 3-D (M3D) ICs. To highlight tradeoffs present in these three designs, we perform analyses on power, performance, and area (PPA) and the clock tree. We also model the tier-to-tier interconnection in each 3-D IC methodology and analyze signal integrity (SI) to assess the reliability of each design. From our experiments using the OpenPiton benchmark, the hybrid bonding design shows the best timing improvement of 81.4% when compared to its 2-D counterpart, while microbumping shows the best reliability among 3-D IC designs. Moreover, we expand our study to the commercial processor architecture, which is Arm Cortex-A53, with the new set of 3-D integration options. In addition, we show the microbump assignment methodology to handle a large number of 3-D interconnections in the microbumping 3-D design. We also perform SI on the new set of 3-D intertier/interdie connections to discuss the reliability based on their physical dimensions. With a new benchmark design, the hybrid-bonding 3-D shows the best energy–delay-product (EDP) improvement, which is 25.8% compared to 2-D, and the largest eye-opening among 3-D integration options.

In this paper, we present three commercial-grade 3D IC designs based on state-of-the-art design technologies, specifically micro-bumping (3D die stacking), hybrid bonding (wafer-on-wafer bonding) and monolithic 3D IC (M3D). To highlight trade-offs present in these three designs, we perform analyses on power, performance, and area and the clock tree. We also model the tier-to-tier interconnection in each 3D IC methodology and analyze signal integrity to assess the reliability of each design. From our experiments, hybrid bonding design shows the best timing improvement of 81.4% when compared to its 2D counterpart, while micro-bumping shows the best reliability among 3D IC designs.

The 2-D CMOS process technology scaling may have reached its pinnacle, yet it is not feasible to manufacture all computing elements at lower technological nodes. This has opened a new branch of chip designing that allows chiplets on different technological nodes to be integrated into a single package using interposers, the passive interconnection mediums. However, establishing a high-frequency communication over an entirely passive layer is one of the significant design challenges of 2.5-D systems. In this article, we present a robust clocking architecture for a 2.5-D system consisting of 64 processor cores. This clocking scheme consists of two major components, namely, interposer clocking and on-chiplet clocking. The interposer clocking consists of clocks used to achieve global synchronicity and clocks for interchiplet communication established using the AIB protocol. We synthesized these clocking components using commercial EDA tools and analyzed them using standard tools, on-chip, and package models. We also compare these results against a 2-D design of the same benchmark and another 2.5-D clocking architecture. Our experiments show that the absolute clock power is up to 16% less, and the ratio of clock power to system power is up to 4% less in the 2.5-D design than its 2-D counterpart.

The optimal selection of an interposer substrate is important in 2.5D systems, because its physical, material and electrical characteristics govern the overall system performance, reliability and cost. Several materials have been proposed that offer various tradeoffs including silicon, organic, glass and etc. In this paper, we conduct a quantitative comparison between two 2.5D IC designs based on silicon vs. liquid crystal polymer (LCP) interposer technologies in the overall system level for the first time. We also investigate tradeoffs in power, performance and area (PPA), signal integrity (SI) and power integrity (PI) depending on the interposer technologies. Through our flow, we generate a large-scale benchmark architecture with commercial-grade GDS layouts of interposer and chiplets using two different interposer substrates. Then, we model transmission lines and power delivery network (PDN) of each 2.5D IC design. Finally, we perform PPA analysis, SI and PI on both 2.5D IC designs to observe the quantitative tradeoffs between two designs. Our experiment shows that silicon interposer-based design has 10.46% less power, 0.25× smaller area and 0.57× shorter average wirelength compared to LCP interposer-based design. However, LCP-based design has 0.59× smaller PDN DC impedance and 0.75× shorter worst delay of interposer wire while maintaining the power delivery efficiency. Lastly, our cost analysis of 2.5D IC design indicates that the overall cost of organic LCP technology, if both the chiplets and their interposer costs are combined, is 2.69× higher than the silicon even the cost of LCP interposer is 1.91% of silicon interposer. This indicates that LCP technology is prohibitive unless the interconnect and bump dimensions are dramatically reduced.

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-onchip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs 1.29× power and 2.19× area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs.

This article addresses the nonlinear behavioral modeling of tunable drivers with preemphasis including power supply noise. The proposed model relies on the use of state-aware weighting functions that control the transitions of the driver's output stage for the scenarios where switched input logic states are shorter than the preemphasis duration, and the influence of supply voltage variation is considered. For the power supply noise analysis, the method is applied to multiple ports. Feedforward neural networks (FFNNs) are used to implement the state-aware weighting functions, and recurrent neural networks (RNNs) are used to capture the dynamic memory characteristics of driver's ports. For tunable drivers in the state-of-the-art design covering features such as drive strength and preemphasis, a parameterized model that considers driver control parameters is presented. As a black-box approach, the resulting model protects intellectual property (IP). Practical industrial driver examples demonstrate the good accuracy, flexibility, and significant simulation speedup of the proposed model, which can facilitate the signal and power integrity (SIPI) analysis.

This article proposes a bit-time-dependent behavioral model of input-output (I/O) drivers for overclocking simulation. The driver behavior under overclocking conditions is investigated, and the corresponding weighting function response surface is demonstrated. In contrast to the previous approaches that use fixed timing signals extracted under normal operating conditions only, the proposed model addresses the modeling of overclocking behavior by using bit-time-dependent weighting functions (BTDWFs) along with a transition variable. The weighting coefficients can be generated appropriately for different overclocking scenarios. The corresponding model extraction flow is presented. Using the proposed BTDWFs, the driver input signal is processed during run-time by a finite state machine (FSM) algorithm which can be implemented in the widely supported hardware description languages such as Verilog-A. The proposed model is able to capture the driver's behavior accurately under both normal operation and overclocking conditions. Its fidelity and simulation speedup are validated with modeling examples using commercial driver circuit.

A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paper we present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.

High-performance low-cost flexible hybrid electronics (FHE) are desirable for internet of things (IoT). Carbon-nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility (25cm2/V.s), superior mechanical flexibility/stretchability, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers and sense amplifiers, can be printed and integrated with thinned (<;50μm) silicon chips on soft, thin, and flexible substrates for appealing product designs and form factors. Here we report: 1) process design kit (PDK) to enable FHE design automation, from device modeling to physical verification, and 2) open-source and solution-process proven intellectual property (IP) blocks, including Pseudo-CMOS [1] digital logic and analog amplifiers on flexible substrates, as shown in Figure 1. The proposed FHE-PDK and circuit design IP are fully compatible with silicon design EDA tools, and can be readily used for co-design with both CNT-TFT circuits and silicon chips.

Integrated voltage regulators (IVR) with embedded inductors is an emerging technology that provides point-of-load voltage regulation to high-performance systems. Conventional two-step approaches to the design of IVRs can suffer from suboptimal design as the optimal inductor depends on the characteristics of the buck converter (BC). Furthermore, inductor-level trade-offs such as AC and DC resistance, inductance and area can not be determined independently from the BC. This co-dependency of the BC and the inductor creates a highly non-linear response surface, which raises the necessity of co-optimization, involving multiple time-consuming electromagnetics (EM) simulations. In this paper, we propose a machine learning based optimization methodology that eliminates EM simulations from the optimization loop to significantly reduce the optimization complexity. A novel technique named as Spectral Transposed Convolutional Neural Network (S-TCNN) is presented to derive an accurate predictive model of the inductor frequency response using a small amount of training data. The derived S-TCNN is then used along with a time-domain model of the BC to perform multi-objective optimization that approximates the Pareto front for 5 objectives, namely inductor area, BC settling time, voltage conversion efficiency, droop and ripple. The resulting methodology provides multiple Pareto optimal inductors in an efficient and fully automated fashion, thereby allows to rapidly determine the optimal trade-offs for possibly contradicting design objectives. We demonstrate the proposed framework on co-optimization of solenoidal inductor with magnetic core and BC that are integrated on silicon interposer.

Digital LDOs enable on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Their design synthesizability with automatic placement and routing can enable per-core DVFS with quick design turnaround. To enable per-core voltage regulation, this paper showcases a digital LDO designed in 65nm CMOS process. The LDO exhibits core-level high load current driving capability of up to 125mA and a large voltage regulation range of 0.15V to 1.15V. The design employs asynchronous nonlinear control to achieve fast voltage droop mitigation under large load transient events. Measurements show a peak current efficiency of 99.9% and greater than 99.5% at a light load of only 4mA and 1nF load decoupling capacitance.

Determination of the data dependent jitter and its effect on the eye diagram is a challenging task in modern high-speed links; therefore, novel statistical approaches are required to expedite this task. Most of the current methods for jitter estimation are only applicable to linear systems, while nonlinear components play an essential role in the high-speed link response. Therefore, this paper introduces a new data dependent jitter estimation approach by using stochastic analysis. In this approach generalized Polynomial Chaos theory is utilized, where linear regression is used to create surrogate models for the link. Statistics of the output signal and jitter calculation are then directly obtained from these models. Two numerical examples are provided to evaluate the efficiency and accuracy of the proposed approach showing good match with the traditional transient eye analysis with good speedup.

Increasing levels of system integration pose difficulties in meeting design specifications for high-performance systems. Oftentimes increased complexity, nonlinearity, and multiple tradeoffs need to be handled simultaneously during the design cycle. Since components in such systems are highly correlated with each other, codesign and co-optimization of the complete system are required. Machine learning (ML) provides opportunities for analyzing such systems with multiple control parameters, where techniques based on Bayesian optimization (BO) can be used to meet or exceed design specifications. In this paper, we propose a new BO-based global optimization algorithm titled Two-Stage BO (TSBO). TSBO can be applied to black box optimization problems where the computational time can be reduced through a reduction in the number of simulations required. Empirical analysis on a set of popular challenge functions with several local extrema and dimensions shows TSBO to have a faster convergence rate as compared with other optimization methods. In this paper, TSBO has been applied for clock skew minimization in 3-D integrated circuits and multiobjective co-optimization for maximizing efficiency in integrated voltage regulators. The results show that TSBO is between 2×-4× faster as compared with previously published BO algorithms and other non-ML-based techniques.

The 3-D integration helps improve performance and density of electronic systems. However, since electrical and thermal performance for 3-D integration is related to each other, their codesign is required. Machine learning, a promising approach in artificial intelligence, has recently shown promise for addressing engineering optimization problems. In this paper, we apply machine learning for the optimization of 3-D integrated systems where the electrical performance and thermal performance need to be analyzed together for maximizing performance. In such systems, modeling can be challenging due to the multiscale geometries involved, which increases computation time per iteration. In this paper, we show that machine learning can be applied to such systems where multiple parameters can be optimized to achieve the desired performance using the minimum number of iterations. These results have been compared with other promising optimization methods in this paper. The results show that on an average, 4.4%, 31.1%, and 6.9% improvement in temperature gradient, CPU time, and skew are possible using machine learning, as compared with other methods.

Over the last several years, the buzzword in the electronics industry has been “More than Moore”, referring to the embedding of components into the package substrate and stacking of ICs and packages using wirebond and package on package (POP) technologies. This has led to the development of technologies that can lead to the miniaturization of electronic systems with coining of terms such as SIP (System in Package) and SOP (System on Package). More recently, the semiconductor industry has started focusing more on 3D integration using Through Silicon Vias (TSV). This is being quoted as a revolution in the electronics industry by several leading technologists. 3D technology, an alternative solution to the scaling problems being faced by the semiconductor industry provides a 3rd dimension for connecting transistors, ICs and packages together with short interconnections, with the possibility for miniaturization, as never before. The semiconductor industry is investing heavily on TSVs as it provides opportunities for improved performance, bandwidth, lower power, reduced delay, lower cost and overall system miniaturization. However, 3D integration poses several challenges related to managing signal, power and thermal integrity - three aspects of the problem that are pristine for ensuring system performance. In addition testing such integrated and miniaturized systems can be challenging as well. In this talk, a few approaches for managing signal, power and thermal integrity are presented in the context of 3D integration along with a few approaches for test and characterization.

3D integration becomes promising to be able to continue the system integration trend due to short TSV interconnection used for stacked dies. This paper proposes an efficient transient thermal modeling method using non-conformal domain decomposition approach for 3D stacked ICs and systems. To alleviate the problem arising from the feature scale difference between stacked dies as well as package and PCB, the 3D system is divided into many subdomains. Each subdomain (die, package or PCB) can be meshed independently using different gridding based on its feature size and therefore the required meshing cells are greatly reduced compared to conventional method such as finite element or finite volume method. The heat flow continuity between subdomains is captured using the introduced interface basis functions. In addition, the proposed compact micro-fluidic model based on finite volume method is proved to be compatible with the finite element model for solid medium based on introduced forced convection boundary and energy conservation. The experimental results show the proposed method offers up to 5x unknown reduction and 91x speed-up compared to conventional finite element method.

This paper proposes a new self-healing methodology for embedded RF amplifiers in RF sub-systems. The proposed methodology is based on oscillation principles in which the device-under-test (DUT) generates its test signature with the help of additional circuitry. In the proposed methodology, the self-generated test signature from the RF amplifier is analyzed by using on-chip resources for testing and controlling its calibration knobs to compensate for multi-parameter variations in the manufacturing process. Thus, the proposed methodology enables self-test and self-calibration/correction of RF amplifiers without the need for an external test stimulus, enabling true self-healing RF designs. The proposed methodology is demonstrated through simulations as well as measurements performed on an RF LNA, which were designed in a commercially-available SiGe BiCMOS process technology.

As the feature size of integrated circuits shrinking in deep submicron technologies, time delay, and crosstalk noise of complementary metal-oxide-semiconductor (CMOS)-gate-driven interconnects become critical issues. Traditionally, CMOS driver is simplified as a linear circuit in which a constant resistance is used to approximate the nonlinear and time-varying MOS resistance, which is inaccurate for signal integrity analysis in high-speed interconnect systems. This paper proposes a finite-difference time-domain (FDTD)-based method for transient analysis of lossy transmission lines in the presence of the nonlinear behavior of CMOS gates. The conventional FDTD with second-order accuracy is used for interconnect analysis and the parameters with frequency-dependent losses are also included. The nonlinear behavior of CMOS gates is represented by alpha-power law model, with the drain current described by piecewise linear function of the drain voltage and discretized in time domain for the FDTD implementation. Explicit forms of the boundary conditions are derived from the implicit interface equations and hence the stability is strictly constrained by Courant condition. Experimental results show that the proposed method has good accuracy and high efficiency with respect to HSPICE. Therefore, it is useful for accurate prediction of time delay and crosstalk noise in high-speed interconnect systems.

This paper proposes a self-calibrating approach for embedded RF down-conversion mixers. In the proposed approach, the output of the RF mixer is analyzed by using on-chip resources for testing and the mixer performs self-compensation for parametric defects using tuning knobs. The tuning knobs enable the RF mixer to self-calibrate for multi-parameter variations induced due to process variability. Using this methodology, it is demonstrated that performance compensation of RF down-conversion mixers can be performed simultaneously for critical specifications such as Gain and 1-dB compression point (P1dB).

This paper proposes a novel self-healing methodology for embedded RF Amplifiers (LNAs) in RF sub-systems. The proposed methodology is based on oscillation principles in which the Device-under-Test (DUT) itself generates the output test signature with the help of additional circuitry. The self-generated test signature from the DUT is analyzed by using onchip resources for testing the LNA and controlling its calibration knobs to compensate for multi-parameter variations in the LNA manufacturing process. Thus, the proposed methodology enables self-test and self-calibration of RF circuits without the need for external test stimulus. The proposed methodology is demonstrated through simulations as well as measurements performed on a RF LNA.

Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS technologies that result in significant yield loss. To this effect, post-manufacture tuning for yield recovery is now a necessity for many high-speed electronic circuits and systems and is typically driven by iterative test-and-tune procedures. Such procedures create new challenges for manufacturing test and built-in self-test of advanced mixed-signal/RF systems. In this paper, key test challenges are discussed and promising solutions are presented in the hope that it will be possible to design, manufacture and test ¿truly self-healing¿ systems in the near future.

For the successful electrical design of system-in-package, this paper proposes an efficient method for extracting wideband resistance and inductance from a large number of 3-D interconnections. The proposed method uses the modal equivalent network from the electric field integral equation with cylindrical conduction-mode basis function, which reduces the matrix size for large 3-D interconnection problems. Additional enhancement schemes proposed further reduce the cost for computing the partial inductances. Therefore, the method discussed in this paper can be used to construct accurate models of a large number of 3-D interconnection structures such as more than 100 bonding wires used for stacking chips.

Low-cost testing of integrated RF substrates is necessary to reduce their production cost. In this paper a new low-cost test approach is proposed for testing an integrated RF substrate with embedded RF passive filters. As compared to a conventional test method the proposed test method reduces the test-setup cost by around 40%. The proposed method enables testing of embedded RF filters by one-port measurement. Also, this method does not require a vector network analyzer and allows testing of these embedded RF circuits without any external test stimulus. Hence, this method brings about a significant reduction in the test cost. The proposed method uses a shift in the oscillation frequency of the test setup for testing embedded filters, but it does not require reconfiguration or conversion of filters into an oscillator as it is done in conventional oscillation-based test methods. The core principle of the method is to include embedded passive filters through one-port substrate surface probe into an external RF oscillator, located on the probe card. Such one-port probing causes a shift in the oscillation frequency of the oscillator because of the loading from the RF filter. The failures in the RF filter are detected by monitoring the shift in the oscillation frequency of the RF oscillator. The test method is demonstrated with both simulations and measurements. Also, wafer-level testing of an integrated RF substrate is illustrated.

The work targets contemporary analog circuits/systems that trend toward high speed mixed analog/digital chips in the multi-GHz range and sub-systems containing both analog and high-speed digital die/chips. In these cases, power integrity is important. For example, for GHz circuits, it can become necessary to block high frequency noise components from radiating or coupling to the analog power plane. Otherwise, operation of sensitive analog blocks or critical signals can be degraded.

In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This is to reduce the simultaneous switching noise (SSN), generated due to the switching activity of digital drivers. Typically this reduction in impedance is accomplished by placing decoupling capacitors between the power and ground planes of a package or board. However, the performance of the decoupling solution is a function of capacitor selection and its placement. In this paper, an automatic capacitor placement optimization method has been proposed. This method relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM). The technique has been employed to show optimized placements for split planes as well as for a realistic multi-layer server board.

For the modeling of interconnect in three-dimensional packagings, this paper proposes a method based on the electric field integral equation (EFIE) with cylindrical conduction mode basis functions (CMBF). The bases are defined to describe arbitrary skin and proximity effects, and partial impedances are obtained from the formulation of the EFIE with CMBF's. Examples of several 3-D interconnects verify that the proposed method is efficient in speed and memory.

Power integrity simulation for system-on-package (SoP) based modules is a crucial bottleneck in the SoP design flow. In this paper, the multi-layer finite difference method (M-FDM) augmented with models for split planes has been proposed as a fast and accurate frequency domain engine. Results demonstrating the accuracy and scalability of the method have been presented. In particular, the algorithm was employed to the analysis of a realistic 6 layer package with ~ 200k nodes.

Physical layout generation of RF embedded passive design is not an easy task since the response of a given layout is tightly coupled with the response of the individual components and the effect of interconnect parasitics. In this paper we propose a methodology for automatic layout generation of embedded passive RF circuits. We make use of circuit models to represent and optimize a given layout and use non-linear optimization at various stages of the methodology to obtain the desired goals. Full-wave EM simulations is completely out of the design loop, so our methodology significantly reduces the design time for RF embedded passive circuits. The proposed approach has been used successfully to generate layout for band-pass filters of varying sizes.

We present a method for fast analysis of signal and power integrity based on a recently developed multilayered finite difference method (M-FDM). In order to accurately model multilayered planar structures, which are three dimensional, M-FDM combines two-dimensional models for power/ground planes using a multilayered unit cell approach. In this way, noise coupling can be considered not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. For a cosimulation of signal and power integrity, transmission line models also need to be included. The interaction between the signal transmission and power distribution modes is taken into account using a modal decomposition technique. An equivalent circuit model becomes available based on this finite difference approximation as well. Based on this network representation, second order effects such as fringe and gap fields can be included in M-FDM using equivalent circuit models for these fields. This results in a very accurate method that can be used for fast analysis of signal and power integrity in arbitrary package and board designs having any stack-up configuration and number of layers.

This paper describes a methodology for performing system level signal and power integrity analyses of SiP-based systems. The paper briefly outlines some new modeling and simulation techniques that have been developed to enable the proposed methodology. Some results based on the application of this methodology on test systems are also presented.

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.

Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the micro-architectural impact of using multiple PLLs for clock distribution. Two PLL phase synchronization algorithms are presented and analyzed. They are compared in terms of efficiency, performance, and complexity. For both, the micro-architectural impact is small, but certainly not negligible.

In this paper, we propose a novel test technique for fault detection and automated fault diagnosis using pole/zero analysis of embedded integrated passive. For pole/zero analysis, an ensemble of circuits obtained by perturbing the circuit under test parameters using their known statistical distributions is generated. The poles and zeros of every circuit in this ensemble are extracted. From knowledge of the passive circuit specifications, pass and fail regions for the critical poles and zeros are computed in the real-imaginary plane. The proposed test technique uses a region-matching algorithm to detect faults and perform automated diagnosis of catastrophic and parametric faults using frequency domain 2-port measurements.

Consistent with industry needs for low-cost MCM substrate test methods, we have earlier developed a single-probe technique for detecting near-opens and near-shorts in substrate interconnects. In this paper we show how a fault-dictionary can be used to accurately determine defect location, size, etc. Such information may be used to perform repair of MCM substrates.

This paper describes a novel and low-cost technique for detecting process-related interconnect faults in MCMs. This method is an alternative to existing test methods such as TDR, TDT electron beam, and capacitance techniques which are either expensive in terms of test equipment, are cumbersome due to the requirement of multiple probes, or provide poor fault coverage. The proposed technique applies a stimulus through a tuned load and a single probe at one end of the interconnect. By measuring the attenuation of the test stimulus due to pole movement relative to known attenuation measurements, interconnect faults such as near-opens, near-shorts, opens, and shorts can be detected. The total test time is small and the hardware cost of test equipment is low. Extensive simulations have been performed to show the validity of the method.