HDLRuby is a new hardware description language defined as an extension of the Ruby programming language aiming to improve circuit design productivity. HDLRuby allows to model digital circuits at the register transfer level while supporting high-level paradigms comprising object-oriented programming, genericity, metaprogramming, and reflection. By construction, HDLRuby can also execute any code in Ruby and supports all of its libraries. Yet, even if high-level features are beneficial for design productivity, such advantages can be negated if the design tools are not efficient enough for producing in reasonable time quality hardware. This article investigates this issue by presenting the techniques used for compiling HDLRuby descriptions and by evaluating their performance. In detail, it explains how the language has been implemented and how it is translated to synthesizable Verilog HDL. Experiments are then presented for confirming the productivity gain of using HDLRuby and for evaluating the performance of the translation, the size of the resulting code, and the time required by a commercially available synthesis tool to produce an FPGA configuration from it. The HDLRuby descriptions used for the experiments include a set of repetitive designs for single construct evaluations and the implementation of generic convolution neural networks for real-life applications. For these evaluations, the translation time proves to be more than 10 times shorter than the synthesis time.

This paper presents a hybrid compile and run-time memory management technique for a 3D-stacked reconfigurable accelerator including a memory layer composed of multiple memory units whose parallel access allows a very high bandwidth. The technique inserts allocation, free and data transfers into the code for using the memory layer and avoids memory overflows by adding a limited number of additional copies to and from the host memory. When compile-time information is lacking, the technique relies on run-time decisions for controlling these memory operations. Experiments show that, compared to a pessimistic approach, the overhead for avoiding overflows can be cut on average by 27%, 45% and 63% when the size of each memory unit is respectively 1kB, 128kB and 1MB.

This paper presents a new technique for reducing the energy consumption of a multi-task system by sharing its scratchpad memory (SPM) space among the tasks. With this technique, tasks can interfere by using common areas of the SPM. However, this requires to update these areas during context switches, which involves considerable overheads. Hence, an integer linear programming formulation is used at compile time for finding the best assignment of memory objects to the SPM and their respective locations inside it. Experiments show that the technique achieves up to 85% energy reduction with 8Kb of SPM and surpasses other sharing approaches.

This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitives to build complex architectures from basic components. This bottom-up approach allows design-architects to explore efficient custom solutions with best performances. This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. The system specifications are represented as a virtual architecture described in a SystemC-like model and annotated with a set of configuration parameters. Our component-based design environment provides automatic wrapper-generation tools able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect API. This approach, experimented over a VDSL system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.

To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The method generates the OS simulation models with the simulation environment as a virtual processor Since the generated OS simulation models use final OS code, the presented method can mitigate the OS code equivalence problem. The generated model also simulates different types of processor exceptions. This approach provides two orders of magnitude higher simulation speedup compared to the simulation using instruction set simulators for SW simulation.

We propose a method of automatic generation of application specific operating systems (OS's) and automatic targeting of application software. OS generation starts from a very small bur yet flexible OS kernel. OS services, which are specific to the application and deduced from dependencies between services, are added to the kernel to construct the whole OS. Communication and synchronization functions in the application code are adapted to the generated OS. As a preliminary experiment, we applied the proposed method to a system example called token ring system.

Software (SW) parts become crucial in embedded systems. Operating systems (OSs) are often used to handle SW concurrency and communication. We propose a method of automatic generation of application-specific OSs and automatic targeting of application SW. OS generation starts from a very small, but yet flexible OS kernel. OS services, which are specific to the application and deduced from dependencies created by the system specification, are added to the kernel to construct the whole OS. Communication and synchronization functions in the application code are adapted to the generated OS. As experiments, we applied the proposed method to two system examples: a token-ring system and a very high data-rate digital subscriber line framer.

Summary form only given. With the rising complexity of electronic systems, containing more and more both hardware and software parts, it becomes necessary to simulate simultaneously hardware and software parts at whatever abstraction level. These simulation techniques, called co-simulation, require fast and flexible simulators. In this paper we introduce the elaboration of a microcontroller simulator for an accurate hardware/software co-simulation at the clock-cycle level. It is our goal to have a simulator which is fast enough to simulate a few minutes of real time execution within a reasonable lapse of time. To be more precise, we deal here with the realization of a simulator for the ST10 microcontroller and its integration into a co-simulation environment.