Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Satoshi Tazawa

dblp:84/3272 · DBLP profile ↗
← Back
2ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › technology computer-aided design
process simulation		 0.011997
A high-speed 2-D topography simulator based on a pixel model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › technology computer-aided design › process simulation
topography simulation		 0.011997
A high-speed 2-D topography simulator based on a pixel model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997

Methods — techniques the papers use, named apart from their topics

x-windows · 0.0pixel model · 0.0
YearPublicationVenuePosition
1997 A high-speed 2-D topography simulator based on a pixel model
abstract
A high-speed two-dimensional (2-D) topography simulator which operates in X-Windows has been developed. This program, named TIGER (Topography Image GEneration Routine), uses a newly developed pixel model, in which regions of the same material are depicted by pixels with the same value (i.e. the same color) and material boundaries are regarded as color boundaries. New cross-sectional profiles are sequentially created by drawing basic geometrical figures on a cross-sectional profile of a former process step. No complex operations are required for boundary line definition, such as loop removal. Realistic cross sections of an LSI with three interconnection layers and an SST transistor with a complex structure were created by this simulator. The total simulation time is only one or two minutes for all the processing steps of an LSI.
Satoshi Tazawa, Katsuyuki Ochiai, Seitaro Matsuo, Shigeru Nakajima
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1984 A Flexible Database System and Its Application in VLSI Process Development
Kou Wada, Satoshi Tazawa, Katsutoshi Kubota
 ITC2