In this article we want to show root causes in semiconductor memory fails which occur despite extensive state of the art testing methodologies. Such fails typically occur in customer applications and when these fails are returned to the original semiconductor manufacturer for retest they are very hard to find or even undetectable. We investigate such fail mechanisms and postulate methods how to detect and remedy them during test as to restore trust into secure semiconductor performance. Finally, we show the implementation of a new test system which has been developed to prove concepts in practice.

With the scaling down of the transistor technology, intrinsic gains of the devices are continuously dropping. Meanwhile, high-gain operational transconductance amplifiers (OTAs) using technologies with reduced feature sizes are required in various applications. This article presents a 55-nm-fabricated three-stage OTA with a single cascode Miller capacitor for driving large capacitive loads. To achieve a high dc gain, a gain enhancement (GE) circuit is used in the first stage to boost the overall voltage gain to above 100 dB. To obtain a stable frequency response, a cascode Miller compensation scheme together with the GE circuits are used to push the nondominant complex pole to higher frequency and adjust the$Q$-factor. The proposed three-stage OTA is implemented in a 55-nm low-power (LP) CMOS process and occupies an area of 0.005 mm2. A current consumption of$157 \mu \text{A}$can be measured with a supply voltage of 1.2 V. The measured results show that this three-stage OTA can achieve stable frequency and transient step responses when driving 2.5-to-30-nF capacitive loads. With a 15-nF capacitive load, a gain bandwidth (GBW) of 0.82 MHz, a phase margin (PM) of 53°, an average slew rate of 0.13 V/$\mu \text{s}$, and an average 1% settling time of$2.62 \mu \text{s}$can be achieved.

The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not.

The authors present new ideas in the field of multilevel optimization for automatic logic macrocell synthesis. The proposed new approach performs a quasi parallel optimization of very different and complex tasks via a simulated annealing based expert system. A true design space exploration is achieved, finding the best solution with respect to a certain cost-function which takes into account actual design parameters like speed, area, power, and not only indirect parameters like number of literals, etc. A small prototype software system had been implemented and it is shown how this new approach, e.g. can be used within a module generator.>

The authors propose a new approach to high level behavioural synthesis starting from an algorithmic description in Hardware C. The algorithm is compiled into a corresponding data/control flow graph including several optimizations. The behavioural synthesis part of the system performs transformations like loop unrolling, parallelization, etc., whereby the user is supported through a feedback loop. For final structural synthesis an advanced tool based on genetic algorithms is provided. Layout synthesis is assumed to be performed by available tools like the GENESIL silicon compiler.>

The authors describe implementation details of a CAD tool for efficient hardware realization of highly parallel algorithms. The Array Specification Language (ASL) of the tool allows the VLSI designer to specify the input not only at dependence graph level, but also at signal/data flow graph and/or array architecture level. Core of this tool is a multilevel functional-structural simulator, embedded into an environment supporting array processor design for real world applications. Another aspect of the tool is the intended support of advanced fault tolerance techniques in an early design phase. More emphasis is given to fabrication-time/run-time fault tolerance techniques and to find a cost-effective solution with the evaluation of optimality criteria and real design tradeoff.>