GPU and FPGA-based clouds have already demonstrated the promise of accelerating computing-intensive workloads with greatly improved power and performance. In this paper, we examine the design of ASIC Clouds, which are purpose-built datacenters comprised of large arrays of ASIC accelerators, whose purpose is to optimize the total cost of ownership (TCO) of large, high-volume chronic computations, which are becoming increasingly common as more and more services are built around the Cloud model. On the surface, the creation of ASIC clouds may seem highlyimprobable due to high NREs and the inflexibility of ASICs. Surprisingly, however, large-scale ASIC Clouds have already been deployed by a large number of commercial entities, to implement the distributed Bitcoin cryptocurrency system. We begin with a case study of Bitcoin mining ASIC Clouds, which are perhaps the largest ASIC Clouds to date. From there, we design three more ASIC Clouds, including a YouTube-style video transcoding ASIC Cloud, a Litecoin ASIC Cloud, and a Convolutional Neural Network ASIC Cloud and show 2-3 orders of magnitude better TCO versus CPU and GPU. Among our contributions, we present a methodology that given an accelerator design, derives Pareto-optimal ASIC Cloud Servers, by extracting data from place-and-routed circuits and computational fluid dynamic simulations, and then employing clever but brute-force search to find the best jointly-optimized ASIC, DRAM subsystem, motherboard, power delivery system, cooling system, operating voltage, and case design. Moreover, we show how data center parameters determine which of the many Pareto-optimal points is TCO-optimal. Finally we examine when it makes sense to build an ASIC Cloud, and examine the impact of ASIC NRE.

This paper describes a novel processor architecture, the prioritized SMT architecture with the IPC control method, to guarantee the execution time of real-time threads. Based on priority set by a real-time scheduler, all hardware resources including cache systems, fetch, issue, and execution units, are controlled, so that our processor can execute multiple threads in real-time. All runnable threads are simultaneously executed as much as possible in priority order, so that the execution order becomes congruent with the priority order set by a real-time scheduler. If a resource conflict occurs, the lower priority threads are kept waiting until the higher priority thread finishes using the resource. In brief, context switching required for real-time scheduling and execution is converted to the prioritized SMT execution. Here, some triggers including cache misses and branch prediction misses fluctuate the execution speed of a thread. Additionally, in case of an SMT processor, the execution time of each thread may vary according to a combination of simultaneous executing threads. To guarantee the execution time of real-time threads accurately, the IPC control method that monitors and controls each thread IPC in a feedback loop is designed and implemented. Our IPC control method can keep the IPC deviation of the thread within plusmn1% bounds, if the target IPC is less than 80% of the single thread execution IPC. Our processor is implemented as a processing core of a system LSI, which process was TSMC 0.13 mum 8 layered Cu wiring, used for distributed real-time systems including humanoid robots, bilateral robots, embedded control systems, and ubiquitous computing systems