We propose Sci-Fii, a speculative conversational interface framework for incremental inference on modularized services. To build one's own conversational interface with existing business logic, cloud-based modularized services offer a suite of ready-to-use components to ease development, ensure cross-platform flexibility, and encapsulate computational complexities. However developing with the modularized services often results in a chain of discrete modules with limited inter-module data sharing, which yields unnecessarily long response times of the conversational interface, aggravates user experiences, and eventually harms user retention. Sci-Fii offers a uniform framework that enables existing serviced modules to benefit from intermediate data and early parallel execution. Transparent to developers, Sci-Fii helps the end-to-end conversational interface system work fluidly and exhibit faster and more natural response times.

Big data is now a ubiquitous part of life — both in test and in many other areas. This talk discusses some of the big problems facing us in test and looks at analogous problems outside of the test domain. It aims to both step back and abstract test-specific problems into general problems and point out similarities and contrasts between test and non-test problems. It also highlights interesting aspects of applying some test-like techniques in non-test settings such as cognitive computing.

One of the most apparent trends in test research and application in recent years has been the increasing application of statistical methods and machine learning. The trend has been driven by factors such as increases in data volume, need to detect subtle defects and need to extend beyond test's traditional sort function to a feedback-providing, yield-learning role. These factors, in turn, reflect needs for efficient data handling, ability to extract small signals from noise, and practically-useful model-building. Similar needs exist in other fields of emerging interest including unstructured text analysis, which in turn supports myriad applications. This paper surveys analysis techniques that have been used in the test domain, draws parallels in unstructured text analysis and suggests insights similar to those used to meet recent test challenges can find application in diverse and emerging fields as well.

Technology scaling introduces many sources of variability and uncertainty that are difficult to model and predict [3]. The result of these uncertainties is a degradation in our ability to predict the performance of fabricated chips, i.e., a lack of model-to-hardware matching. The prediction of circuit performance is the result of a complex hierarchy of models starting at the basic MOSFET device model and rising to full-chip models of important performance metrics like power, frequency of operation, etc. The assessment of the quality of such models is an important activity, but it is becoming harder and more complex with rising levels of variability, as well as with the increase in the number of systematic effects observed in modern CMOS processes. The purpose of this paper is to introduce a special-purpose test structure that specifically focuses on ensuring the accuracy of gate timing models. The certification of digital design correctness (the so-called signoff) is based largely on the results of performing a Static Timing Analysis (STA) [15], [18], which, in turn, is based entirely on the gate timing models. Our test structure compares favorably to alternative approaches; it is far easier to obtain the desired results than direct delay measurement, and it is much more general than simple ring oscillator structures. Further, the structure is specified at a high level, allowing it to be synthesized using a standard ASIC place-and-route flow, thus capturing the systematic local layout effects which can sometimes be lost by simpler (e.g., ring oscillator) structures. Experimental results show the structure can play an important role in identifying mismatches between timing models and observed hardware.

In the nanometer era, the mismatch between the pre-silicon model and the post-silicon timing behavior is becoming severer. Therefore, it is necessary to validate timing with post-silicon data. We propose a method that estimates all the segment delays in the observed paths of a design from post-silicon path delay measurements. Our method is based on equality-constrained least squares methods, which enable us to find a unique and optimized solution of segment delays from underdetermined systems. Experimental results show that segment delays obtained using our method achieved correlation ranged from 0.848 to 0.992 to the sampled segment delays for different ISCAS-85 benchmark circuits.

This paper proposes methods for taking advantage during voltage-based production test of the capability to control well and substrate (body) biases separately from the chip's VDD and GND. Such control is a by-product of a low-power design strategy that allows parts or all of the chip to go into low-power reduced-leakage states. The proposed test methods use body bias manipulation to increase or decrease transistor threshold voltages. Unlike related methods that rely on weakening transistors, the proposed methods are shown to enhance defect detectability by both weakening and strengthening transistors and by exploiting the ability to weaken/strengthen nfets/pfets separately.

As gains in integrated circuit power and performance achieved through scaling of feature sizes slows, system and circuit design must carry more of the burden for improvement. Aggressive design decreases guardbands, increasing the risk of circuit failure. This paper discusses the increasing need for embedded on-chip sensors to enable aggressive design and also to help counter the attendant increased risks.

Timing analysis is a key sign-off step in the design of today's chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing behavior that will be seen in actual product silicon. As a result, it is necessary to validate timing models in silicon. Traditional ways to validate timing models use ring oscillators or perform delay testing but both approaches have significant drawbacks. Ring oscillators lack diversity in circuit structure and present layout configurations that are not typical of real products. Delay test can be expensive to apply and provides directly only path delay information not individual gate delays. To address these limitations, we explore the potential of a new test structure-based method of timing model validation. The proposed approach combines benefits of a ring oscillator and path delay testing while addressing their limitations. Specifically, the test structure is composed of circuits that are physically synthesized and therefore product-representative, but configures the devices under test into oscillating paths so that measurement is easy and inexpensive. Path delay test ATPG is used to generate test patterns whose oscillation frequencies provide measures of path delays. Gate delays are deduced from those path delays using a matrix that codes the delay elements comprising each path in a careful way that overcomes overdetermination problems in the matrix algebra. Results show that RMS errors can be maintained under 5% for all gate types using a chosen circuit.

This paper provides an overview of chip-level failure mechanisms and test screens. Emphasis is placed on detectability of defect mechanisms by chip-level test, trends that affect failure mechanisms and screens, and resulting implications for system-level yield and reliability.

The complexity of interactions in todaypsilas manufacturing processes makes test structures and experiments inadequate as sole drivers of yield-learning and design-for-manufacturing [DfM]. They must be driven by product impact. Product-impact-oriented test-based learning provides insight into the nature of model-hardware mismatches and variability that exist on and impact real products. That insight can be used to drive both parametric and defect-oriented process actions and DfM.

Manufacturing process variability compromises design aggressiveness, yield and system-level power-performance. This paper presents strategies for unraveling variability to understand its sources so that appropriate corrective action can be applied. The strategies are applied to data representing operation of finished electronic circuits, including product test results on real product hardware.

The failure mechanisms that occur on manufactured ICs affect yield or, worse, shipped product quality level. The difference between the two is in whether or not detection occurs at test. In this talk, we look at the types of failure mechanisms that occur, including random contamination-related defects, systematic defects and systematic parametric variations. We go through an evidence round-up looking empirically at defect occurrences in yesterday's and today's chips and discuss trends for the future. Implications of the various failure mechanisms on detectability at test are discussed and both failure mechanism occurrence and detectability are considered as drivers for DFM.

A methodology based on canonical views is developed to facilitate rapid analysis of CMOS characterization and test data for product and process debug. The compressed representations aid in both quantitative and intuitive assimilation of the data, with a focus on model-to-hardware correlation and manufacturing variability

Detecting real defects, increases the fabrication facility's urgency to eliminate the source of the defect and gives assurance to the customer that the quality enhancement process is in action. Such satisfying moments may be more and more rare, however, as challenges to the physical failure analysis process make it increasingly difficult to get such pictures and as failure modes themselves become less amenable to the same. As challenges to physical failure analysis increasingly relegate it to a sampling/verification role, opportunities such as innovative use of process monitors and test structures and circuit-behavior/simulation-based pointers to failure root cause must increasingly be exploited and increasingly trusted as high-fidelity guide to yield learning.

This work demonstrates IDDQ signature analysis of random and systematic defects, including yield detractors and reliability defects. Application is demonstrated for both understanding failure root cause and guiding test decisions. IDDQ signatures contain rich information about the circuit, defect behavior and processing conditions. This paper describes capturing that information by classifying signatures into different categories and using the classifications to learn about the nature of the defects occuring on a variety of ASIC chips.

Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.

Transient signal analysis (TSA) is a testing method that is based on the analysis of a set of V/sub DD/ transient waveforms measured simultaneously at each supply port. Defect detection is performed by applying linear regression analysis to the time or frequency domain representations of these signals. Chip-wide process variation effects introduce signal variations that are correlated across the individual power port measurements. In contrast, defects introduce uncorrelated local variations across these measurements that can be detected as anomalies in the cross-correlation profile derived (using regression analysis) from the power port measurements of defect-free chips. This paper focuses on the application of TSA to the detection of delay faults.

A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulation experiments are designed to determine the effects of process skew (obtained from measured parameters of a real process) on the accuracy of TSA in estimating path delays from power supply I/sub DDT/ and V/sub DDT/ waveforms. The circuit model is designed to test TSA under deep submicron process models that incorporate advanced parameters such as transistor V/sub t/ width dependencies. Modeling elements of a testing environment including the probe card are subsequently introduced as a means of evaluating the effects of tester measurement noise in an actual implementation.

A delay-fault testing strategy based on the analysis of power supply transient signals is presented. The method is an extension to a Go/No-Go device testing method called Transient Signal Analysis (TSA). TSA detects defects through the analysis of a set of power supply transient waveforms in the time or frequency domain, e.g., Fourier phase components. A recent extension to TSA demonstrated a correlation between the V/sub DDT/ Fourier phase components and path delays in defect-free devices. The method proposed here is able to detect increases in delay due to resistive shorting and open defects using a similar technique. In particular simulation results show that a delay defective device can be distinguished from a defect-free device through an anomaly in the Fourier phase correlation profile of the device.

Understanding the effectiveness of their production tests is a critical task for IC suppliers. Numerous trends suggesting that conventionally applied test methods must change to meet future needs will make the task even more critical-and difficult-in the future. This paper presents characterization and diagnostic data and ideas aimed at helping IC suppliers understand test effectiveness.

Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Application of current signatures in die selection and defect diagnosis is discussed as well.

This paper investigates the important question of whether or not Iddq-only fails are "bad" and should be rejected during testing. The analysis is based on the Sematech experiment results and employs current signature-based testing.

Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Application of current signatures in die selection and defect diagnosis is discussed as well.

Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first step of this study involved development of a new DFT cost/benefit trade-off modeling procedure. Next, the developed cost model (which we call the CMU Test Cost model) was used, with a range of parameters representing typical industrial conditions, to answer the question: to DFT or not to DFT. The obtained results indicate that in the DFT application space there exist regions in which one can provide a clear answer to this question. There also exist regions of uncertainty. One of the objectives of our study has been to identify ways of minimizing this uncertain region.

In this paper we demonstrate that performing I/sub DDQ/ testing against a single threshold current value does not make sense. In place of the single current threshold we propose the "current signature". A die's current signature takes into account the relative measured level of current on all applied I/sub DDQ/ vectors. Preliminary results of current signature applications are discussed as well.

This paper analyzes the feasibility of MCMs using active silicon substrates with built-in resting circuitry. It identifies the domain of applicability of such MCMs and points to limitations of the "Known Good Die" approach.