This paper presents new, fast hardware for computing the exponential function, sine, and cosine. The main new idea is to use low-precision arithmetic components to approximate high precision computations, and then to correct very quickly the approximation error periodically so that the effect is to get high precision computation at near low-precision speed. The algorithm used in the paper is a nontrivial modification of the well-known CORDIC algorithm, and might be applicable to the computation of other functions than the ones presented.

Present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. This approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.>

The author shows how to design one-level carry-skip adders that attain very high speeds. One-level carry-skip adders are very fast adders that are hardly more complex than the much-slower ripple adders. The design procedure allows the use of realistic component delays obtained by simulation and is technology-independent. An example of a 64-b, 1 mu m CMOS adder is given. This adder achieves an add time of 6.23 ns, measured by SPICE simulation with realistic loads. This delay figure excludes sum buffering delays, which depend on the particular application of the adder. The combination of high-speed and simplicity makes one-level carry-skip adders attractive for applications in highly parallel systems.>

This paper describes a new type of carry-skip adder, which can be faster than the conventional two-level carry-skip adders. A way to design optimum adders of this new type is described. In optimum adders of this type, the sizes of the sections of bit positions are bimodal, but the sizes of the blocks in each section are unimodal, unlike the bimodal block sizes in Guyot et al.'s traditional two-level carry-skip adders. A 60-b 2- mu m CMOS adder of this type is designed. This adder's simulated delay is approximately 12.6 ns.>

The author presents a very fast adder for double-precision mantissas, which is an improvement on T. Lynch and E. E. Swartzlandes, Jr.'s spanning tree carry lookahead adder or redundant cell adder (see ibid., vol. 41, 1992) which was implemented using the Am29050 microprocessor. The adder presented is faster than theirs mainly because Manchester carry chains of various lengths are used instead of chains all of the same length.>

A method for designing optimum-speed one-level carry-skip adders is described. This method always yields the fastest adders if the assumptions of A. Guyot et al. (1987) hold, that is if the ripple time (a circuit parameter) of a carry signal is a linear function of the number of bit positions that the carry signal propagates through, and if the skip time (another circuit parameter) of a carry signal is a linear function of the number of blocks of bit positions skipped by the signal, or if these two parameters are such mildly nonlinear functions that can be modeled by a linear function without any effect on any of the results obtained. The circuit design method is useful because in device technologies such as 2-AlU CMOS the nonlinearities are often insignificant. The present results are compared with those of Guyot et al. as well as with the results of V.G. Oklobdzija and E.R. Barnes (1985).>

Problems related to the movement of n-link robot arms in two dimensions are considered. We present an algorithm, requiring O(n) computation time, which moves an arm confined in a circular region to any reachable configuration in O(n) moves. Also given is an O(n) computation time algorithm that computes all the regions reachable by the joints of such an arm. These results are improvements over the cubic algorithms of Hopcroft, Joseph, and Whitesides (SIAM J. Comput.14, No. 2 (1985)). We finally show how to plan motion involving the minimum number of moves for an arm in the obstacle-free plane in O(n3) computational steps.