EDBT 2026 Demo / reviewers in the wild / expert
Yi Qian 0003
dblp:84/4625-3
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2020
0000-0003-1063-1853ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Performance modeling and evaluation · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
0.4 | 1 | 2020 | Online Firmware Functional Validation Scheme Using Colored Petri Net Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Performance modeling and evaluation
petri net modeling |
0.4 | 1 | 2020 | Online Firmware Functional Validation Scheme Using Colored Petri Net Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.4colored petri nets · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Online Firmware Functional Validation Scheme Using Colored Petri Net ModelabstractFirmware functional validation suffers from a series of performance limitations in practice, which in turn heavily relies on manual effort and becomes a major bottleneck of product time cycle. The requirement of repetitive run-time firmware execution for the validation environment demands novel techniques to accelerate the validation process. We propose an online firmware functional validation scheme utilizing the colored Petri net (CPN) model which can be generated automatically from the firmware source code. With simulation runs on the generated CPN models at run-time, the firmware execution path is presented and, if an error occurs, the location of error can be identified. An integrated validation tool has been designed and implemented to show the proposed validation methodology's potential and effectiveness. This tool is used in the validation of the universal serial bus (USB) initialization in unified extensible firmware interface (UEFI). Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Yi Qian 0003, Rahul Khanna |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |