A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptographic device, is presented. The proposed circuit exploits the relative jitter between two identical ring oscillators sharing the same delay elements and shows several advantages with respect to other oscillator-based generators reported in the technical literature. In particular, the generator is stateless and therefore easily testable accordingly to what is reported in (Bucci, 2005). Moreover, the generation throughput is automatically adapted to the available noise in the circuit thus guaranteeing the statistical quality (minimum entropy) of the generated bits. To validate the proposed circuit, simulation results on a 0.12mum CMOS process are reported

The design of a high-speed IC random number source macro-cell, suitable for integration in a smart card microcontroller, is presented. The oscillator sampling technique is exploited and a jittered oscillator which features an amplified thermal noise source has been designed in order to increase the output throughput and the statistical quality of the generated bit sequences. The oscillator feedback loop acts as an offset compensation for the noise amplifier, thus solving one of the major issues in this kind of circuit. A numerical model for the proposed system has been developed which allows us to carry out an analytical expression for the transition probability between successive bits in the output stream. A prototype chip has been fabricated in a standard digital 0.18 /spl mu/m n-well CMOS process which features a 10 Mbps throughput and fulfills the NIST FIPS and correlation-based tests for randomness. The macro-cell area, excluding pads, is 0.0016 mm/sup 2/ (184 /spl mu/m /spl times/ 86 /spl mu/m) and a 2.3 mW power consumption has been measured.