Today's, a promising solution, namely wireless network‐on‐chip (WiNoC) is utilized in multi‐core systems to overcome the constraints of conventional on‐chip networks. In WiNoC architectures, wireless routers (WRs) provide high capacity wireless links to reduce the latency of multi‐hop communications. However, the buffer size of the WR antenna is limited, and under heavy traffic loads, it's filled and congestion occurs. On the other hand, network performance is degraded severely in the presence of head‐of‐line (HOL) blocking. Therefore, flow control and scheduling mechanisms are vital for improving the performance of WiNoCs. In this study, a flow control scheme based on an active queue management algorithm, and a priority‐based scheduling strategy are suggested. The proposed mechanisms are evaluated under uniform and Bit‐complement traffic patterns with different packet injection rate. The simulation results show that the proposed schemes have a significant impact on performance parameters, such as latency and throughput. Moreover, the saturation packet injection rate in WiNoC with four WRs is improved to about 33% under uniform traffic and is increased up to about 50% under the Bit‐complement traffic pattern. This is increased by 16 and 50% in WiNoC with 16 WRs for uniform and Bit‐complement traffic patterns, respectively, compared to the conventional WiNoCs.

The interaction between cores and memory blocks, in multiprocessor chips and smart systems, has always been a concern as it affects network latency, memory capacity, and power consumption. A new 2.5-dimensional architecture has been introduced in which the communication between the processing elements and the memory blocks is provided through a layer called the interposer. If the core wants to connect to another, it uses the top layer, and if it wants to interact with the memory blocks, it uses the interposer layer. In a case that coherence traffic at the processing layer increases to the extent that congestion occurs, a part of this traffic may be transferred to the interposer network under a mechanism called load balancing. When coherence traffic is moved to the interposer layer, as an alternative way, this may interfere with memory traffic. This paper introduces a mechanism in which the aforementioned interference may be avoided by defining two different virtual channels and using multiple links which specifically determines which memory block is going to be accessed. Our method is based on the destination address to recognize which channel and link should be selected while using the interposer layer. The simulation results show that the proposed mechanism has improved by 32% and 14% latency compared to the traditional load-balancing and unbalanced mechanisms, respectively.

Abstract Radio frequency identification grouping proof authentication protocol is an approach to identify a set of tagged objects simultaneously. Over the past decade, several protocols in this domain have been presented, but each was weak with flawed attributes. It is essential that a grouping proof protocol be both scalable and affordable, considering its use for applications with large quantities of tags and the high level of security. In this paper, we present a secure and scalable grouping proof protocol by utilizing an encryption method that is called authenticated encryption. This encryption method provides both confidentiality and message integrity simultaneously. In addition, it can satisfy the resource limitation of passive tags. The proposed protocol eliminates the dependency among the tags' responses and provides the scalability with minimum message broadcasting. We evaluate the proposed protocol based on formal and informal security methods, and the results prove that it is robust against radio frequency identification attacks and suitable for low‐power and low‐cost devices. Copyright © 2017 John Wiley & Sons, Ltd.

As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NIs). In this paper, we present a set of data encoding schemes aimed at reducing the power dissipated by the links of an NoC. The proposed schemes are general and transparent with respect to the underlying NoC fabric (i.e., their application does not require any modification of the routers and link architecture). Experiments carried out on both synthetic and real traffic scenarios show the effectiveness of the proposed schemes, which allow to save up to 51% of power dissipation and 14% of energy consumption without any significant performance degradation and with less than 15% area overhead in the NI.

In this paper, we propose a novel mapping algorithm for providing Quality of Service (QoS) under bandwidth constraints in 3D Network-on-Chip (NoC). The QoS is warranted in such a way that all minimum feasible paths considering the required and available bandwidth are explored by the mapping algorithm. The maximum required bandwidth on the network links for this mapping algorithm is compared with other methods such as NMAP, Onyx and Citrine while applied on two video processing applications i.e. VOPD (Video Object Plane Decoder) and MPEG-4. The available bandwidth of vertical and horizontal links are considered the same and different in the experimental results.

NoC performance largely depends on the underlying deadlock-free and efficient routing algorithm. Selection strategies play a pivotal role in the effectiveness of the routing algorithm by selecting the final output channel when there is more than one possible output link returned by an adaptive routing. In this paper a novel selection strategy, LATEX, is proposed that can be used with any adaptive routing algorithm for specified applications. The objective of the proposed selection strategy is to efficiently balance traffic load and reach better performance results. Performance evaluation is carried out by using a flit-accurate simulator under two real traffic scenarios. Result experiments show that the proposed selection strategy applied to several routing algorithms significantly improves average delay, max delay and power consumption.

Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future embedded systems. The performance of NoC largely depends on the underlying deadlock-free and efficient routing algorithm. When the adaptive routing returns a set of acceptable output channels, then a selection strategy is used to select the output channel, therefore the selection strategy affects the efficiency of adaptive routing. In this paper a novel selection strategy for avoiding congested areas using a fuzzy-based routing decision is proposed that can be used with any adaptive routing algorithm. The objective of the proposed selection strategy is to choose a channel that has more free slots input buffer and lower power consumption. The routing path is established by minimizing a cost which is calculated by fuzzy controller and considers the power consumption and free slots input buffer of cores. Performance evaluation is carried out by using a flit-accurate simulator under different traffic scenarios. Result experiments show that the proposed selection strategy applied to Odd-Even routing algorithm can effectively improves average delay and power consumption to meet power balance requirement and avoid hotspot with low hardware overhead.