Article Interconnect analysis: from 3-D structures to circuit models Share on Authors: M. Kamon Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , N. Marques Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , Y. Massoud Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , L. Silveira Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , J. White Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 910–914https://doi.org/10.1145/309847.310097Online:01 June 1999Publication History 8citation278DownloadsMetricsTotal Citations8Total Downloads278Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Accurate interconnect analysis has become essential not only for post-layout verification but also for synthesis. This tutorial explores interconnect analysis and extraction methodology on three levels: coarse extraction to guide synthesis, detailed extraction for full-chip analysis, and full 3D analysis for critical nets. We will also describe the electrical issues caused by parasitics and how they have, and will be, influenced by changing technology. The importance of model order reduction will be described as well as methodologies at the synthesis stage for avoiding parasitic problems.

As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate three-dimensional interconnect models. In this paper, we describe an integral equation aproach to modeling the impedance of inter-connect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior: Our formulation, based on a combination of nodal and mesh analysis, has the required properties to be combined with Model Order Reduction techniques to generate accurate and guaranteed passive low order Interconnect models for efficient inclusion in standard circuit simulators. Furthermore, the formulation is shown to be more flexible and efficient than previously reported methods.

As VLSI circuit speeds have increased, the need for accurate three-dimensional interconnect models has become essential to accurate chip and system design. In this paper we describe an integral equation approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors. Unlike previous methods, our approach is based on a modified nodal analysis formulation and can be used directly to generate guaranteed passive low order interconnect models for efficient inclusion in a standard circuit simulator.

In this paper we describe a computationally efficient approach to generating reduced-order models from PEEC-based three-dimensional electromagnetic analysis programs. It is shown that a recycled multipole-accelerated approach applied to recent model order reduction techniques requires nearly two orders of magnitude fewer floating point operations than direct techniques thus allowing the analysis of larger, more complex three-dimensional geometries.

This paper demonstrates the use of three-dimensional electromagnetic field solvers to accurately model the interconnect for a 2.4 GHz RF to IF Converter integrated circuit under development at Harris Semiconductor.Lumped element RLC models for the package leads, bondwires, die attach plane, and on-chip interconnect are shown to provide accurate simulation versus measurement and prove the importance of modeling the entire packaged IC.

Since the first papers on asymptotic waveform evaluation (AWE), Pade-based reduced order models have become standard for improving coupled circuit-interconnect simulation efficiency. Such models can be accurately computed using bi-orthogonalization algorithms like Pade via Lanczos (PVL), but the resulting Pade approximates can still be unstable even when generated from stable RLC circuits. For certain classes of RC circuits it has been shown that congruence transforms, like the Arnoldi algorithm, can generate guaranteed stable and passive reduced-order models. In this paper we present a computationally efficient model-order reduction technique, the coordinate-transformed Arnoldi algorithm, and show that this method generates arbitrarily accurate and guaranteed stable reduced-order models for RLC circuits. Examples are presented which demonstrates the enhanced stability and efficiency of the new method.

Since the rst papers on asymptotic waveform evaluation (AWE), reduced order models have become standard for improving interconnect simulation eciency, and very recent w ork has demonstrated that bi-orthogonalization algorithms can be used to robustly generate AWE-style macromodels.In this paper we describe using block Arnoldi-based orthogonalization methods to generate reduced order models from FastHenry, a m ultipole-accelerated three dimensional inductance extraction program.Examples are analyzed to demonstrate the eciency and accuracy of the block Arnoldi algorithm.

In [1], it was shown that an equation formulation based on mesh analysis can be combined with a GMRES-style iterative matrix solution technique to make a reasonably fast 3-D frequency dependent inductance and resistance extraction algorithm. Unfortunately, both the computation time and memory required for that approach grow faster than n/sup 2/, where n is the number of volume-filaments. In this paper, we show that it is possible to use multipole-acceleration to reduce both required memory and computation time to nearly order n. Results from examples are given to demonstrate that the multipole acceleration can reduce required computation time and memory by more than an order of magnitude for realistic packaging problems.

The combination of a mesh analysis equation formulation technique with a preconditioned GMRES matrix solution algorithm to accelerate the determination of inductances of complex three-dimensional structures is described. Addition of the preconditioner to GMRES can reduce the cost of solution to m/sup 2/ operations compared to m/sup 2/ for direct inversion. Results from FASTHENRY, a 3-D inductance extraction program, demonstrate that the iterative approach can accelerate solution times by more than an order of magnitude.>