In this paper, we introduce the Tensor Streaming Processor (TSP) architecture, a functionally-sliced microarchitecture with memory units interleaved with vector and matrix deep learning functional units in order to take advantage of dataflow locality of deep learning operations. The TSP is built based on two key observations: (1) machine learning workloads exhibit abundant data parallelism, which can be readily mapped to tensors in hardware, and (2) a simple and deterministic processor with producer-consumer stream programming model enables precise reasoning and control of hardware components, achieving good performance and power efficiency. The TSP is designed to exploit parallelism inherent in machine-learning workloads including instruction-level, memory concurrency, data and model parallelism, while guaranteeing determinism by eliminating all reactive elements in the hardware (e.g. arbiters, and caches). Early ResNet50 image classification results demonstrate 20.4K processed images per second (IPS) with a batch-size of one— a $4 \times$ improvement compared to other modern GPUs and accelerators [44]. Our first ASIC implementation of the TSP architecture yields a computational density of more than 1 TeraOp/s per square mm of silicon for its $25 \times 29$ mm 14nm chip operating at a nominal clock frequency of 900 MHz. The TSP demonstrates a novel hardware-software approach to achieve fast, yet predictable, performance on machine-learning workloads within a desired power envelope.

Manufacturing test equipment used to test multi-Gb/s input/output signals is typically expensive, and costs are expected to rise dramatically as data rates on these signals get even faster. The problem is further exacerbated by a rapid increase in the number of chip pins dedicated to interfaces that require such high-speed signals. Many recent interface specification standards for SERDES, PCI Express, USB, DDR, SATA, etc. demand performance parameters that seem nearly impossible to test in a high volume manufacturing (HVM) test environment. Adaptive design techniques, ECC, proper characterization, and a well-balanced system design approach using DFT in harmony with practical fixturing and ATE configurations can provide a cost-effective environment for economical manufacturing test of multi-Gb/s I/O signals.

Test automation has been a cornerstone of the manufacturing test industry, much as electronic design automation has been to the semiconductor industry. Thus, it is fair to say that test automation providers will have a significant role to play in addressing the challenges involved in testing system-chips of the future. This session contains presentations that examine the test challenges presented by system-level integration, from the perspective of the providers of test tools and methodologies. The presenters will highlight innovations that will lead to improved test flows, addressing critical issues such as testing cost, test application time, and reuse of test hardware for silicon debug.

Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation whose result is not used in the downstream circuit, power is being consumed for an otherwise redundant computation. Operand isolation is a technique to minimize the power overhead incurred by redundant operations by selectively blocking the propagation of switching activity through the circuit. This paper discusses how redundant operations can be identified concurrently to normal circuit operation, and presents a model to estimate the power savings that can be obtained by isolation of selected modules at the register-transfer (RT) level. Based on this model, an algorithm is presented to iteratively isolate modules, while minimizing the cost incurred by RTL operand isolation. Experimental results with power reductions of up to 30% demonstrate the effectiveness of the approach.

No abstract available.