A primary aim of Coarse-Grained Reconfigurable Arrays (CGRAs), compared to FPGAs, is to maximize the portion of the die used for computational resources, while minimizing the complexity of control and steering logic, leading to inherently constrained routing architectures. This challenge has compelled CAD developers to utilize exact solutions, such as integer linear programming (ILP), in formulating and solving the mapping problem. Those solutions have been shown not to scale, especially for larger devices with intricate architectural features, such as multiple contexts and optional pipeline registers. Even if an exact or a greedy approach yields a feasible solution, it often fails to optimize multifaceted objective criteria. In this work, we have devised a framework for systematically enumerating mapping solutions of a subject kernel on a target CGRA using Zero- Suppressed Binary Decision Diagrams (ZDDs). To effectively manage runtime, we developed a linear algorithm that retains the best$k$solutions at each stage of the mapping flow, where both the objective function and$k$are user defined. Experimental results on a diverse range of application kernels targeting two CGRA architectures show how we can enumerate hundreds of thousands of solutions within seconds. When compared against prior methodologies, and while generating dozens of solutions, our mapper exhibits a remarkable speed advantage, ranging from one to three orders of magnitude faster than exact and heuristic approaches. Notably, when allocated the same runtime as the fastest heuristic, our framework demonstrates its efficacy by generating an impressive 105 solutions.

The restricted routing networks of coarse-grained reconfigurable arrays (CGRAs) have motivated CAD developers to utilize exact solutions, such as integer linear programming (ILP), in formu-lating and solving the mapping problem. Such so-lutions that rely on general purpose optimizers have not been shown to scale. In this work, we formu-late CGRA mapping as a solution enumeration and selection problem, relying on the efficiency of zero-suppressed binary decision diagrams (ZDDs) [22] to capture the solution space. For small-to-moderate size problems, it is possible to capture every possible map-ping in a few megabytes. For larger problems, thou-sands if not millions of solutions can be enumerated. The final mapping is a simple linear-time DAG traver-sal of the enumeration ZDD. The proposed solution was implemented in the CGRA-ME [6] framework. A speedup of two orders of magnitude was obtained when compared with past solutions targeting smaller CGRA devices. Larger devices beyond the capacity of those solutions are now accessible.

Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware platforms that can be used to realize application-specific accelerators for higher performance and energy efficiency. A CGRA is a 2D array of configurable logic blocks & interconnect, where the logic blocks are typically large & ALU-like, and the interconnect is word-wide. CGRA-ME is a software framework that enables the modelling and exploration of CGRA architectures, as well as research on CGRA CAD algorithms. With CGRA-ME, an architect can specify a CGRA architecture at a high level of abstraction. A set of applications can be mapped onto the architecture to assess the mappability, power, performance and cost. CGRA-ME also allows one to generate synthesizable Verilog RTL for the modelled CGRA, permitting its implementation as an ASIC or FPGA overlay. In this paper, we describe the CGRA-ME framework [5] and overview its capabilities and current limitations. We discuss ongoing and prior research conducted with the framework, as well as outline future plans. We believe CGRA-ME will be a valuable contribution to the community, enabling new research on CGRA CAD & architectures.

Variations of list scheduling became the de-facto standard of scheduling straight line code in software compilers, a trend faithfully inherited by high-level synthesis solutions. Due to its nature, list scheduling is oblivious of the tightly coupled register pressure; a dangling fundamental problem that has been attacked by the compiler community for decades, and which results, in case of highlevel synthesis, in excessive instantiations of registers and accompanying steering logic. To alleviate this problem, we propose a synthesis framework called soft scheduling, which acts as a resource unconstrained pre-scheduling stage that restricts subsequent scheduling to minimize register pressure. This optimization objective is formulated as a live range minimization problem, a measure shown to be proportional to register pressure, and optimally solved in polynomial time using minimum cost network flow formulation. Unlike past solutions in the compiler community, which try to reduce register pressure by local serialization of subject instructions, the proposed solution operates on the entire basic block or hyperblock and systematically handles instruction chaining subject to the same objective. The application of the proposed solution to a set of real-life benchmarks results in a register pressure reduction ranging, on average, between 11% and 41% depending on the compilation and synthesis configurations with minor 2% to 4% increase in schedule latency.

Simulated annealing has became the de facto standard for FPGA placement engines since it provides high quality solutions and is robust under a wide range of objective functions. However, this method will soon become prohibitive due to its sequential nature and since the performance of single-core processor has stagnated. General purpose computing on graphics processing units (GPGPU) offers a promising solution to improve runtime with only commodity hardware. In this work, we develop a highly parallel approach to simulated annealing-based placement using GPGPU. We identify the challenges posed by the GPU architecture and describe effective solutions. An average speedup of about 10× was achieved over conventional placement within 3% of wirelength.

The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the departure from the industrial standard, register transfer level design methodology. Recent advances of micro-architecture model enabled the use of stacked based controller, allowing complex algorithms with multiple procedures to be implemented directly in hardware. Nevertheless, design optimizations across procedure boundaries have not been fully explored. In this paper, we address the problem of interprocedural register allocation in the context of high level synthesis. In contrast to a recently proposed interprocedural register allocation algorithm, which processes an expensive, global, graph representation of the conflict relation of all values to achieve near optimality, we introduce a new method, called color palette propagation (CPP). The key idea behind our method, is to propagate the use of colors, whose number is significantly smaller than the size of the conflict relation, across different procedures. With a complexity comparable to intraprocedural register allocation, we show that our method can scale to very large C programs. For those benchmarks that can be handled by conventional global methods, our method produced nearly the same number of registers, while providing an average speedup factor of 90.