We present a framework called Hierarchically Interacting Logs (HIL) for constructing Flash Translation Layers (FTLs). The main goal of the HIL framework is to heal the Achilles heel —the crash recovery—of FTLs (hence, its name). Nonetheless, the framework itself is general enough to encompass not only block-mapped and page-mapped FTLs but also many of their variants, including hybrid ones, because of its compositional nature. Crash recovery within the HIL framework proceeds in two phases: structural recovery and functional recovery. During the structural recovery, residual effects due to program operations ongoing at the time of the crash are eliminated in an atomic manner using shadow paging. During the functional recovery, operations that would have been performed if there had been no crash are replayed in a redo-only fashion. Both phases operate in an idempotent manner, preventing repeated crashes during recovery from causing any additional problems. We demonstrate the practicality of the proposed HIL framework by implementing a prototype and showing that its performance during normal execution and also during crash recovery is at least as good as those of state-of-the-art SSDs.

Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.

MIMO-OFDM system significantly improves the data rates over wireless channels. V-BLAST is well known effective technique which enhances the system performance while allowing low implementation complexity. However, the performance of V-BLAST technique would be degraded by the error propagation due to the nulling and canceling process. In order to improve the performance of V-BLAST, this paper proposes spatial diversity technique combined with rotated constellation for MIMO-OFDM systems. It is demonstrated in the simulation evaluation that the proposed technique can offer excellent performance with spatial diversity gain in time-varying typical urban channel.

This paper introduces a novel data synchronization method for ATSC distributed translator (DTxR) to improve the indoor reception performance of DTV (Digital TV). The proposed method extracts the frame sync information from the received RF signal and utilizes it for constructing the rebroadcast signal of DTxR. Computer Simulations are performed for the basic working algorithm of prototype system and some practical application issues are described.

Multiple input multiple output (MIMO) system provides a promising means to increase the spectral efficiency. Orthogonal frequency division multiplexing (OFDM) allows broadband transmission over frequency selective fading channels. Recently, a coordinate interleaver (CI) is considered in order to maximize the diversity gain for MIMO system. In this paper, a new concept of coordinate interleaver for MIMO-OFDM system and an optimum receiver structure are suggested. Using the CI, the real and imaginary components of signals experience different fading channels and it provides additional diversity gains. Simulation results show that the system employing the proposed CI outperforms the conventional V-BLAST architecture.

MIMO-OFDM systems would provide both multiplexing gain and diversity gain in order to improve the system capacity and the receive performance. This paper introduces the coordinate interleaved hybrid transmission for use in MIMO- OFDM systems to meet such requirements. The proposed CID- SFBC-OFDM and CID-STBC-OFDM combine the coordinate interleaver with Double SFBC-OFDM and Double STBC-OFDM to achieve additional diversity gain whilst retaining their spatial multiplexing gain. Our simulation results show that CID-SFBC- OFDM and CID-STBC-OFDM outperform the conventional schemes in typical urban (TU) channel.

In this paper, we explain the basics of flash memory technology in general and solid state disks in particular, and describe development platforms specifically designed for flash memory solid state disks.

This paper presents a robust block iterative/adaptive frequency-domain channel estimation scheme, in which a channel frequency response (CFR) is estimated iteratively through the proposed weighted element-wise block adaptive frequency-domain channel estimation (WEB-CE) using the soft information obtained from a soft-input soft-output (SISO) decoder. In the WEB-CE, an one-tap equalizer first structures the element-wise block by assembling its input elements out of discrete Fourier transform (DFT) of the soft information. Then, it updates the correction term of its coefficient in each block so as to minimize a weighted conditional squared-norm of the a posteriori error vector defined for the element-wise block. Simulation results verify the superiority of the WEB-CE in a time-varying typical urban (TU) channel.

In this paper, a weighted space-time block-coding (STBC)-like matrix-wise block adaptive frequency-domain equalization (WSB-FDE), which has a flexibility over the STBC-like matrix-wise block length as compared to a normalized least- mean-square (NLMS)-FDE and a recursive-least-square (RLS)- FDE, is proposed for the cyclic-prefixed STBC single-carrier systems equipped with a diversity combining. In the WSB-FDE, the STBC-like matrix-wise block is first formulated from received blocks. The correction terms of the equalizer coefficients in each block are then updated so as to minimize a weighted squared- norm of the a posteriori error vector for the formulated block. Moreover, a square-root adaptive algorithm based on an unitary Givens rotations is proposed to achieve the numerical stability and computational efficiency in update procedure of the WSB- FDE. Finally, simulation results show in a typical urban (TU) channel that the bit-error-rate (BER) performance of the WSB- FDE is superior to that of the RLS-FDE as the STBC-like matrix- wise block length increases.

This paper reviews Flash memory technology and flash translation layer (FTL) that provides a block device interface out of flash memory. It also describes two implementations of FTL that represent two extreme points in the spectrum of cost-performance trade-offs in FTL implementation. After presenting results on the performance and energy- efficiency of the two FTLs, this paper argues for a configurable FTL to address the diversity of mobile embedded systems in terms of cost and performance requirements.