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We present a technique for low power realization of Finite Impulse Response (FIR) filters implemented using Distributed Arithmetic. In most applications, the distribution profile of input data values is known. The proposed technique uses a data encoding which can be tuned to the specific distribution profile so as to reduce toggles in the shift register chain. We present a generic Nega-Binary coding approach and show how a specific Nega-Binary scheme can be derived to achieve maximum power reduction. We also show how the binary to Nega-binary conversion can be performed bit-serially with minimal area (and hence power dissipation) overhead. The paper finally presents a shift-free implementation which uses memory array to store data values. We present a technique based on Gray coded addressing to reduce the power dissipation in such implementations.

This paper addresses the problem of reducing power dissipation of finite impulse response (FIR) filters implemented on programmable digital signal processors (DSPs). We describe a generic DSP architecture and identify the main sources of power dissipation during FIR filtering. We present seven transformations to reduce power dissipated in one or more of these sources. These transformations complement each other and together operate at algorithmic, architectural, logic and layout levels of design abstraction. Each of the transformations is discussed in detail and the results are presented to highlight its effectiveness. We show that the power dissipation can be reduced by more than 40% using these transforms. The transformations have been encapsulated in a framework that provides a comprehensive solution to low-power realization of FIR filters on programmable DSP's.

We present code generation of multiplication-free linear transforms targeted to single-register DSP architectures such as TMS320C2x/C5x. We first present an algorithm to generate optimized code from a DAG representation. We then present techniques that transform a DAG so as to minimize the number of nodes and the accumulator-spills. We then introduce a concept of spill-free DAGs and present an algorithm for synthesizing such DAGs. The results for Walsh-Hadamard, Haar and Slant transforms show 25% to 40% reduction in the cycle count using our techniques.

No abstract available.

In this paper we present optimizing transformations to minimize the number of additions+subtractions in both the direct form (/spl Sigma/ A/sub i/X/sub n-i/ based) and its transposed form (Multiple Constant Multiplication based) implementation of FIR filters. These transformations are based on the iterative elimination of 2-bit common subexpressions in the coefficients binary representations. We give detailed description of the algorithms and present results for eight low pass FIR filters with the number of coefficients ranging from 16 to 128. The results show upto 35% reduction in the number of additions+subtractions to implement /spl Sigma/ A/sub i/X/sub n-i/ based FIR filter structures and upto 38% reduction to implement MCM based structures.

The concept of a conditionally robust two-pattern test for testing stuck-open transistor faults in CMOS gates is introduced. Such a test is conditionally hazard-free; i.e. the transition will not produce a hazardous output provided a (partial) order is imposed on the time instants at which the components of the input pattern undergo transition. Two sources of the existence of such a partial order are identified: (1) when a set of transistors is controlled by the same logic signal, the symbolic layout (routing) information provides the knowledge of such a partial order; and (2) multipattern tests, which may be necessary to test embedded CMOS gates, can be looked upon as two-pattern tests with an imposed partial order. Algorithms are given to determine whether a two-pattern test is conditionally hazard-free under a given partial order and to compute minimal cardinality partial orders that, when imposed on a transition, make it conditionally hazard-free.>