Healthcare data provides a wealth of information that can be used to study and improve patient outcomes. Electronic Medical Records and other sources of healthcare data are often managed in relational database system and archived using modern data warehousing techniques. Contemporary semantic database technology has many advantages over traditional database systems; however, the utility of the semantic data can be limited if the data is not converted properly from a tabular representation. There are a variety of tools which will naively convert tabular data into a Resource Description Format semantic graph. Without proper guidance from the operator, the tools will generate a semantically weak database which doesn't have the necessary richness for semantic analysis. This paper describes the conversion process for two healthcare databases, with the goal of creating a robust dataset for semantic analysis. The “lessons learned” from this process are detailed in order to serve as a resource for other biomedical researchers and clinicians interested in generating a useful semantic dataset from their own relational databases.

Interest in studying human posture, movement, and physical activity is growing due in part to the increasing prevalence of obesity. Accelerometers are commonly used in motion analysis systems to enable researchers to conduct studies outside of the traditional laboratory environment; however the available systems tend to be bulky and unsuitable for long-term studies. Therefore, a need exists for a physically robust, yet compact motion analysis system that can be easily worn for an extended time period without disrupting the person's range of motion. Here we describe our on-going efforts to develop a robust, compact system that can measure body posture and movement using a tri-axial accelerometer, and then store this data on a secure digital memory card. This device can be easily configured to collect accelerometer data for specific applications in human motion analysis. In the future, this device will be used to study physical activity in free-living individuals

The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.

A revolution is occurring in several device and integrated circuit technologies (silicon CMOS and its extensions such as silicon germanium and silicon on insulator [SOI] and the so-called III-V compound semiconductors including indium phosphide and gallium arsenide), as well as in solid-state sensors such as infrared detectors enabled by the new materials and devices. These new components are being used to enhance the performance of many systems, and even to create systems never before available, of present interest to the U.S. Department of Defense and of likely near-term interest to parts of the commercial electronics industry such as the landline, wireless, and satellite telecommunications industry. These new components require advanced electronic packaging that does not restrict or degrade their performance. Unfortunately largely due to commercial cost pressures, research in and small-lot manufacture of high-performance packaging though still feasible and not lacking for good ideas for possible enhancement, are no longer being actively pursued either by the principal U.S. government agencies (e.g., DARPA, Air Force), by the commercial electronic packaging industry, or by commercial consortia such as the Microelectronics and Computer Technology Corporation (defunct as of June 2000), Semiconductor Research Corporation (SRC), or Sematech Inc. This paper discusses recent examples of high-performance components and integrated circuit technologies and describes how they are being exploited in new or upgraded systems. Advances in packaging technology that will be required to support the new integrated circuits are also described. In conclusion, several possible approaches are reviewed by which the United States can regain momentum in the development of performance-driven packaging technologies.

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.

Resonant tunnelling diode based logic circuits offer significant advantages for low power, ultra-high-speed applications. In this work, a low-power resonant interband tunneling diode (RITD)-based logic technology capable of operating at clock rates of at least 12 GHz is reported. The circuits are fabricated using InAs/AlSb/GaSb RITDs. Fanout of at least two at a clock rate of 10 GHz is also reported for two AND gates in a two-stage pipelined configuration. Simulation results for an RITD/HFET circuit based on measured characteristics of InAs/AlSb/GaSb RITDs and InAs-channel HFETs for a simple inverting Schmitt trigger are presented to demonstrate the advantages of an integrated RITD/HFET technology. This circuit architecture demonstrates proper operation with power supply voltages as low as 0.5 V. In addition, well defined logic levels and abrupt logic transitions are achieved, despite the limited transconductance and large output conductance typical of InAs-channel HFETs.

Several computer-aided design (CAD) tools suitable for use by the designers of digital signal and data processors based on the quasi-TEM assumption for multiconductor transmission lines are presented. The integral equation method due to C. Wei, et al. (1984) is selected for the evaluation of electrostatic parameters, including capacitance, inductance, conductance, and resistance matrices, and attenuation factors as well as propagation constants and crosstalk. These parameters are thereafter used to simulate the waveforms of coupled stripline/microstrip lines by the system decoupling method, which is derived in a manner simpler than previously described in the literature. The computer codes along with the graphics input routines have been integrated into a CAD system referred to as MagiCAD, and are suitable for direct use in CAD procedures for the design of high-clock-rate digital circuits. Numerical examples, comparisons, and applications are shown.>

The development of gallium arsenide digital integrated circuit technology has progressed rapidly during the past decade. It is argued that in order to derive the maximum benefit from this technology as it is inserted into next-generation signal and data processors, all aspects of the design, assembly, testing, and maintenance of the systems will have to be considered synergistically. Salient issues which must be considered in the implementation of these advanced digital processors are reviewed, including the effects of system, logic board, chip layout, and packing constraints on memory layout, logic design, and arithmetic implementation.>

Supersystems are general purpose computers achieving throughputs in excess of 1 billion instructions per second (BIPS). As such, supersystems present formidable design challenges in the areas of technology and architecture. This paper examines three of the classical design options: high-speed monoprocessors, array processors, and distributed processors. The latter approach appears most desirable for supersystems, but will require improved interconnection networks.

The first of a new generation of high performance X-ray computed tomographic (CT) machines, the Dynamic Spatial Reconstructor, imposes a requirement for digital signal processing rates which are 3–4 orders of magnitude greater than the capability of current X-ray computed tomography processors. To solve the large-scale computational problems for this and similar CT units which are currently under development, three candidate arithmetic implementations of ultra-high-speed convolutional filtering and weighted linear summation algorithms have been developed and compared. Since both convolution and weighted summation are performed via the inner product operation, which is the basis for most digital signal processing algorithms, the results are widely applicable. The three arithmetic approaches are a two's complement modular array, a merged arithmetic module, and a sign/logarithm convolver. A figure of merit, which relates processing speed to complexity, is used to compare the three arithmetic approaches. It is demonstrated that processing rates in the billions of multiply-add operations per second may be realized with special-purpose processors of moderate complexity.

The inner product computer is a special-purpose computational unit intended to be used as an adjunct to a general-purpose digital computer to perform numerical processing tasks which previously exceeded the capacity of the general-purpose computer. The algorithmic structure of the inner product is briefly reviewed in the first section of this paper. Methods are described for computing the inner product of complex vectors with a series of four real inner products. Several hardware implementations of the inner product computer are described and then compared in terms of speed and complexity; a figure of merit is developed to simplify the comparison. The utility of this computational unit is demonstrated via the examination of a large-scale numerical problem, computerized three-dimensional x-ray reconstruction (computerized tomography) arising in the biomedical sciences. Finally, a comparison is given of the size of a general-purpose computer required to execute a large-scale processing task with that of an inner product computer to execute the same task. The inner product computer greatly reduces computational costs for the solution of a large class of problems, including computerized tomography, image restoration, weather forecasting, and economic modeling.

A memory control unit is described, which, operating in conjunction with a special purpose digital computer, achieves real-time storage into and retrieval from computer memory of individual video images undergoing on-line digitization, processing, and reconstitution. The memory control unit is capable of rapid sequential access on up to six 16 K-word core and two 131 K-word (28-bit word) solid-state memories, achieving data transfers to or from ememory at up to 40 million 9-bit samples/s for 33 ms. The memory control unit employs a variety of data rates, and can, under program control, assemble one or more bytes into, or disassemble one or more bytes from, each memory word. The control unit can sign extend incoming data to any of four different byte lengths from any of four different byte lengths. The control unit possesses dual data busses, one dedicated to memory read operations and a second capable of either "reads from" or "writes into" memory. The eight memory modules are sequenced by a small microprogrammed control store loadable from an associated computer.

A high-fidelity video digitizer/processor extracts spatial and gray-scale information from high resolution dynamic video imagery. The 15-MHz bandwidth 60/s images(fields) are low pass filtered to minimize aliasing and digitized in real-time at 20 million samples pe second (MS/s), 9 bits/sample; sequential fields are transferred to memory, retrieved from memory after computer image processing, and reconstituted at up to 40 MS/s into 60 field/s video of 525, 875, or 1225 lines/frame (two interlaced fields). A/D and D/A converters are synchronized with memory by a high-speed interface, composed of a central data interchange (DI), and 8 rarially connected I/O ports. The DI connects the data paths of one or more ports, each communicating with one or more external devices. Separate 16-bit, 40 megawords/s, input and output data buses between each port and the DI allow data entry through any port to the DI and output from the DI through any port(s), even the same port from which the input originated. The A/D and D/A are served by a single port. Two other ports communicate with CDC 3500 and CDC 1700 computers. Yet another port controls up to two megawords of core/solid-state memory, of which 358K word may be accessed at the full data rate. Storage rates into existing memory of 40 MS/s are achieved for 16-32 ms.