The integration of heterogeneous intellectual property hardware (IP) into existing hardware platforms is often only considered with respect to IP cores that provide bus interfaces to their environment. This paper will show that there is a need for, and an advantage to be gained from, incorporating non-bus interface IP so that they can be used by software running on the platformpsilas processor(s). This paper presents a grammar with which services of non-bus interface cores can be described. The paper will show how this description can be used to generate adapters to integrate the IP as well as device drivers to use the IP. Experiments show how the use of this description can reduce the integration effort of non-bus interface cores.

In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have analysed, which are common in todays system on chip environments, and require to be modelled at a transaction level. Second our findings in terms of the data structures and interface API's that are required in order to model those (and we believe other) busses and IO structures. Third the surrounding infrastructure that we believe can, and should be in place to support the modelling of those busses and IO structures. We will present the infrastructure that we have built, and indicate where our future work will hea.

Our concept of a virtual transaction layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual channels which efficiently route transactions between SW and HW entities through the on-chip communication network with respect to quality-of-service and realtime requirements. The goal is to methodically simplify MPSoC design by systematic HW/SW interface abstraction, thus enabling early SW verification, rapid prototyping and fast exploration of critical design issues. With TRAIN, we present our implementation of such a VTL architecture for Virtex-II Pro and PowerPC and illustrate its efficiency by experimentation