Spiking Neural Networks (SNNs) remain on the fringe of machine learning research despite their potential for fast low-power performance and fully local operation, including rapid online learning, on edge computing devices. In SNNs, encoding information in the timing of individual spikes is more efficient than using spiking rates for which many spikes are required. However, combining spike-time coding with unsupervised learning has proven somewhat challenging. Here we use spike latency coding with local unsupervised spike-timing-dependent plasticity and several biologically inspired local homeostatic mechanisms that maintain network stability. We show that when trained on sequences of characters from text, the network rapidly and effectively self-organizes to learn a latent space mapping of character attributes, similar to word2vec but for characters (i.e. char2vec), forming clusters of vowels, consonants and punctuation for example. It does so with no explicit objective function and no error signal, showing that time-encoded unsupervised SNNs (STUNNs) can maintain dynamical stability while self-organizing to extract complex input relationships using only local learning rules.

This work presents two 4-bit resistor-string digital-to-analog converters (R-DAC) designed in 22nm FDSOI technology. Both DACs are connected to a shared resistor string to make the final layout more compact. The small on-resistance of the Transmission-Gate (TG) switches designed in the FDSOI node yields a low Internal non-linearity (INL) and Differential non-linearity (DNL) in the DACs output. The effect of the temperature variations on the linearity performance of the DACs is also studied. It is shown that the temperature gradients can be compensated for by equally distributing the switches on the layout area. Post-layout simulations show an approximately fixed INL and DNL of, respectively, 0. 17LSB and 0. 1LSB over a wide temperature range from -40°C to $125^{0} C$. Two R-DACs dissipate the static/dynamic power of 0. 12/0.155mW with the layout size of only 70 $\mu m^{2}$, showing a high performance for two 4-bit DACs.

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2.

The inefficiencies of von-Neumann computing architectures in performing high-level machine learning and neuromorphic operations have led to the need for new computational systems such as oscillatory neural networks, that are designed using emerging technologies. The frequency dynamics of Ferroelectric field-effect transistor (FeFET)-based coupled oscillator neurons, as integral parts of these novel computational networks are investigated in this paper. The concept of time to frequency modulation is also introduced which can be used to distinguish dynamical changes in the incoming signals. Simulation results show a significant reduction in power consumption with approximately 9 μW for each oscillator neuron. This is significant improvement over results reported for spin-torque and metal-insulator-migration oxide-based coupled-oscillators. Integrability with CMOS technology in conjunction with lower power consumption and simpler topologies make FeFET devices promising candidates for the next generation of neuromorphic computing platforms, and particularly for image, video, and audio processing tasks.

We propose a biologically inspired binaural sound localization system using a deep convolutional neural network (CNN) for reverberant environments. It utilizes a binaural Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear system to analyze binaural signals, a lateral inhibition function to sharpen temporal information of cochlear channels, and instantaneous correlation function on the two cochlear channels to encode binaural cues. The generated 2-D instantaneous correlation matrix (correlogram) encodes both interaural phase difference (IPD) cues and spectral information in a unified framework. Additionally, a sound onset detector is exploited to generate the correlograms only during sound onsets to remove interference from echoes. The onset correlograms are analyzed using a deep CNN for regression to the azimuthal angle of the sound. The proposed system was evaluated using experimental data in a reverberant environment, and displayed a root mean square localization error (RMSE) of 3.68° in the -90° to 90° range.

For this demonstration, we have implemented a Spiking Neural Network (SNN) on a Field Programmable Gate Array (FPGA) and trained it using Spike Timing Dependent Plasticity (STDP) to identify temporally encoded characters, in an unsupervised manner. The constructed one-layer network consists of plastic excitatory and non-plastic inhibitory synapses, which are connected to output Izhikevich neurons. The implemented neural hardware demonstrates a powerful and fast learning scheme, which brings about a significant unsupervised classification accuracy of 94 %.

Neuromorphic hardware platforms have demonstrated significant promise in cognitive tasks such as visual processing and classification. These platforms usually consist of several layers of spiking neurons for feature extraction and various learning mechanisms, which renders the associated networks power and hardware hungry. In this paper, we have implemented a simplified proof-of-concept Spiking Neural Network (SNN) on a Field Programmable Gate Array (FPGA) and trained it using Spike Timing Dependent Plasticity (STDP) to identify temporally encoded characters, in an unsupervised manner. The constructed one-layer network consists of excitatory synapses, which receive input characters in the form of Poissonian spike trains from the pre-synaptic side. From the post-synaptic side, the synapses are connected to output Izhikevich neurons. In addition, non-plastic inhibitory synapses between the output neurons are introduced to implement lateral inhibition and competitive learning. The implemented neural hardware demonstrates a powerful and fast learning scheme, which brings about a significant unsupervised classification accuracy of 94 %. In addition, since the proposed network receives the characters in the form of spike trains, it is amenable to being interfaced to neuromorphic event-driven sensors such as silicon retina, making the proposed platform useful for online unsupervised template matching applications.

Filters in cochlea models use different coefficients to break sound into a two-dimensional time-frequency representation. On digital hardware with a single sampling rate, the number of bits required to represent these coefficients require substantial computational resources such as memory storage. In this paper, we present a cochlea model operating at multiple sampling rates. As a result, fewer bits are required to represent filter coefficients on hardware as opposed to all the filters operating at a single sampling rate. Additionally, with a 108-filter cochlea implementation, up to nine times fewer coefficients are used than a single sampling rate approach across all filter sections. We present an implementation of 108 filters in Matlab and on an Altera Cyclone V FPGA with a low logic level utilization of 2.57%. Our model can thus be extended to include other auditory processing models such as loudness, pitch perception and timbre recognition on a single FPGA.

We propose a biologically inspired binaural sound localization system for reverberant environments. It uses two 100-channel cochlear models to analyze binaural signals, and each channel of the left cochlea is compared with each channel of the right cochlea in parallel to generate a 2-D instantaneous correlation matrix (correlogram). The correlogram encodes both binaural cues and spectral information in a unified framework. A sound onset detector is used to generate the correlogram only during the sound onsets, and the onset correlogram is analyzed using a linear regression approach as well as an extreme learning machine (ELM). The proposed system is evaluated using experimental data in reverberation environments, and we obtained an average absolute error of 16.5° for linear regression and 12.8° for ELM regression in the -90° to 90° range.

The positive-feedback gain-enhancement operational transconductance amplifier (OTA) design is a promising architecture to scale into deep submicron CMOS. Ever smaller CMOS process nodes require analog circuit designs that can overcome the area-power-matching relation. We introduce a Nauta OTA with a split architecture consisting of fixed width and digitally programmable variable width transconductors utilizing the minimum grid-spacing of the CMOS process enabling an active mismatch cancelation technique. A variation-aware statistical design practice is introduced to analyze the sizing of transconductors, computing code-word solutions for statistically likely solutions, and estimating average maximum dc gain over the entire code-space of many simulated OTAs. Prototypes of a 8-bit differential OTA in 180-nm CMOS designed using the Nauta structure fixed width and digitally programmable variable width architecture achieves an average maximum dc gain of 60 dB, simulated unity gain frequency of 4.6 GHz, and a figure-of-merit of 1 GHz/mW.

We present a digital implementation of the Spike Timing Dependent Plasticity (STDP) learning rule. The proposed digital implementation consists of an exponential decay (exp-decay) generator array and a STDP adaptor array. The weight values are stored in a digital memory, and the STDP adaptor w ill send these values to the exp-decay generator using a digital spike of which the duration is modulated according to these values. The exp-decay generator will then generate an exponential decay, which will be used by the STDP adaptor for performing the weight adaption. The exponential decay, which is computational expensive, is efficiently implemented by using a novel stochastic approach. This stochastic approach was fully analysed and characterised. We use a time multiplexing approach to achieve 8192 (8k) virtual STDP adaptors and exp-decay generators with only one physical adaptor and exp-decay generator respectively. We have validated our stochastic STDP approach with measurement results of a balanced excitation experiment. In that experiment, the competition (induced by STDP) between the synapses can establish a bimodal distribution of the synaptic weights: either towards zero (weak) or the maximum (strong) values. Our stochastic approach is therefore ideal for implementing the STDP learning rule in large-scale spiking neural networks running in real time.

The Nauta structure differential operational transconductance amplifier (OTA) is introduced as a solution to an amplifier design in deep submicrometer CMOS. This simple high-speed inverter-based architecture uses a negative conductance dc gain enhancement technique to produce high dc gains and large unity gain frequencies. The design tradeoff is that the achievable dc gain is proportional to transistor device matching. Our analysis shows that fixed width Nauta structure OTAs have low dc gains due to variations, and thus viable Nauta OTAs need to have tuning mechanisms available to correct for mismatch. This paper presents a digitally programmable Nauta structure OTA architecture built using digital-to-transconductance converters (DTCs). These DTCs are designed to allow for flexibility in producing digital tuning solutions to the device mismatch problem using Nauta OTAs. We present a theoretical analysis of the digital Nauta OTA solution space for high dc gains and a statistical framework to estimate the likelihood of achieving certain gain specifications. Experimental results from a 65-nm CMOS prototype shows that the architecture achieves an average dc gain of greater than 60 dB in line with the minimum expected gain of 59 dB, and on-chip unity gain bandwidth is inferred above 5.8 GHz.

In the biological nervous system, large neuronal populations work collaboratively to encode sensory stimuli. These neuronal populations are characterised by a diverse distribution of tuning curves, ensuring that the entire range of input stimuli is encoded. Based on these principles, we have designed a neuromorphic system called a Trainable Analogue Block (TAB), which encodes given input stimuli using a large population of neurons with a heterogeneous tuning curve profile. Heterogeneity of tuning curves is achieved using random device mismatches in VLSI (Very Large Scale Integration) process and by adding a systematic offset to each hidden neuron. Here, we present measurement results of a single test cell fabricated in a 65nm technology to verify the TAB framework. We have mimicked a large population of neurons by re-using measurement results from the test cell by varying offset. We thus demonstrate the learning capability of the system for various regression tasks. The TAB system may pave the way to improve the design of analogue circuits for commercial applications, by rendering circuits insensitive to random mismatch that arises due to the manufacturing process.

In this paper we present a biologically inspired rotationally-invariant end-to-end recognition system demonstrated in hardware with a bitmap camera and a Field Programmable Gate Array (FPGA). The system integrates the Ripple Pond Network (RPN), a neural network that performs image transformation from two dimensions to one dimensional rotationally invariant temporal patterns (TPs), and the Synaptic Kernel Adaptation Network (SKAN), a neural network capable of unsupervised learning of a spatio-temporal pattern of input spikes. Our results demonstrate rapid learning and recognition of simple hand gestures with no prior training and minimal usage of FPGA hardware.

In this paper we present the Synaptic Kernel Adaptation Network (SKAN) circuit, a dynamic circuit that implements Spike Timing Dependent Plasticity (STDP), not by adjusting synaptic weights but via dynamic synaptic kernels. SKAN performs unsupervised learning of the commonest spatio-temporal pattern of input spikes using simple analog or digital circuits. It features tunable robustness to temporal jitter and will unlearn a pattern that has not been present for a period of time using tunable “forgetting” parameters. It is compact and scalable for use as a building block in a larger network to form a multilayer hierarchical unsupervised memory system which develops models based on the temporal statistics of its environment. Here we show results from simulations as well present digital and analog implementations. Our results show that the SKAN is fast, accurate and robust to noise and jitter.

The front end of the human auditory system, the cochlea, converts sound signals from the outside world into neural impulses transmitted along the auditory pathway for further processing. The cochlea senses and separates sound in a nonlinear active fashion, exhibiting remarkable sensitivity and frequency discrimination. Although several electronic models of the cochlea have been proposed and implemented, none of these are able to reproduce all the characteristics of the cochlea, including large dynamic range, large gain and sharp tuning at low sound levels, and low gain and broad tuning at intense sound levels. Here, we implement the `Cascade of Asymmetric Resonators' (CAR) model of the cochlea on an FPGA. CAR represents the basilar membrane filter in the `Cascade of Asymmetric Resonators with Fast-Acting Compression' (CAR-FAC) cochlear model. CAR-FAC is a neuromorphic model of hearing based on a pole-zero filter cascade model of auditory filtering. It uses simple nonlinear extensions of conventional digital filter stages that are well suited to FPGA implementations, so that we are able to implement up to 1224 cochlear sections on Virtex-6 FPGA to process sound data in real time. The FPGA implementation of the electronic cochlea described here may be used as a front-end sound analyser for various machine-hearing applications.

We will demonstrate a 100-CAR-section cochlear model running in real time on an FPGA. Although our result suggests that an electronic cochlea with 1224 cochlear sections can be implemented on an average FPGA [1], the data rate limit of USB 2.0 does not permit us to implement more than 100 filter sections and display the output on a PC. Future work will explore alternatives to increase the bandwidth such as a PCI interface or USB 3.0 that will enable us to implement more filter sections. Nonetheless, our work demonstrates the capability of the CAR model to process sound in real-time.

We present an FPGA design framework for large-scale spiking neural networks, particularly the ones with a high-density of connections or all-to-all connections. The proposed FPGA design framework is based on a reconfigurable neural layer, which is implemented using a time-multiplexing approach to achieve up to 200,000 virtual neurons with one physical neuron using only a fraction of the hardware resources in commercial-off-the-shelf FPGAs (even entry level ones). Rather than using a mathematical computational model, the physical neuron was efficiently implemented with a conductance-based model, of which the parameters were randomised between neurons to emulate the variance in biological neurons. Besides these building blocks, the proposed time-multiplexed reconfigurable neural layer has an address buffer, which will generate a fixed random weight for each connection on the fly for incoming spikes. This structure effectively reduces the usage of memory. After presenting the architecture of the proposed neural layer, we present a network with 23 proposed neural layers, each containing 64k neurons, yielding 1.5 M neurons and 92 G synapses with a total spike throughput of 1.2T spikes/s, while running in real-time on a Virtex 6 FPGA.

We present a compact mixed-signal implementation of synaptic plasticity for both Spike Timing Dependent Plasticity (STDP) and Spike Timing Dependent Delay Plasticity (STDDP). The proposed mixed-signal implementation consists of an a VLSI time window generator and a digital adaptor. The weight and delay values are stored in a digital memory, and the adaptor will send these values to the time window generator using a digital spike of which the duration is modulated according to these values. The analogue time window generator will then generate a time window, which is required for the implementation of STDP and STDDP. The digital adaptor will carry out the weight/delay adaption using this time window. The aVLSI time window generator is compact (50 μm2in IBM 130nm process) and we use a time multiplexing approach to achieve up to 65536 (64k) virtual digital adaptors with one physical adaptor, consuming only a fraction of the hardware resource on a Virtex 6 FPGA. Since the digital adaptor has been implemented on an FPGA, it can be easily reconfigured for different adaptation algorithms, which leaves it open for future development. Our mixed-signal implementation is therefore practical for implementing the synaptic plasticity in large-scale spiking neural networks running in real time. We show circuit simulation results illustrating both weight and delay adaptation.

We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order log-domain low-pass filters to implement a generalised conductance-based silicon neuron. It consists of a single synapse, which is capable of linearly summing both the excitatory and inhibitory post-synaptic currents (EPSC and IPSC) generated by the spikes arriving from different sources, a soma with a positive feedback circuit, a refractory period and spike-frequency adaptation circuit, and a high-speed synchronous Address Event Representation (AER) handshaking circuit. To increase programmability, the inputs to the neuron are digital spikes, the durations of which are modulated according to their weights. The proposed neuron is a compact design (∼170 µm2in the IBM 130nm process). Our aVLSI generalised conductance-based neuron is therefore practical for large-scale reconfigurable spiking neural networks running in real time. Circuit simulations show that this neuron can emulate different spiking behaviours observed in biological neurons.

As advances in integrated circuit (IC) fabrication technology reduce feature sizes to dimensions on the order of nanometers, IC designers are facing many of the problems that evolution has had to overcome in order to perform meaningful and accurate computations in biological neural circuits. In this paper, we explore the current state of IC technology including the many new and exciting opportunities “beyond CMOS.” We review the role of noise in both biological and engineered systems and discuss how “stochastic facilitation” can be used to perform useful and precise computation. We explore nondeterministic methodologies for computation in hardware and introduce the concept of stochastic electronics (SE); a new way to design circuits and increase performance in highly noisy and mismatched fabrication environments. This approach is illustrated with several circuit examples whose results demonstrate its exciting potential.

This paper presents a flexible solution for performing measurements of internal chip signals at the bench, which reduces overall system costs and test risks. It also makes available a way to insert signals at predefined nodes and to bring the system to a specified state. For this purpose, we use a Serial-to-Parallel Interface (SPI) block with a simple communication protocol, which enables the designer to reconfigure as many internal test structures as desired, as well as to drive different internal signals to or from the chip pads. As these pads are reconfigurable, their number can be reduced to a minimum, which in turn reduces silicon area and die cost. The need to use physically intrusive micro probes is reduced and, most importantly, it allows the possibility to acquire internal signals of fully encapsulated dies.

We present a standard pipelined ADC design using Nauta structure differential op-amps as an alternative to traditional analog op-amps. The six stage pipelined ADC is capable of running at 100MS/s and achieves 8 bit resolution under simulations. The research is focused on the path to scaling to deep sub-micron CMOS and finding alternatives to the reduced gain and low output voltage swing of traditional analog op-amp designs. The Nauta structure op-amp allows us to produce one of the smallest reported areas for a 180nm pipelined ADC occupying only 0.3mm2for a 10 bit 100MS/s pipelined ADC.

We present a voltage domain implementation of a programmable delay axon circuit together with measurements from it. It was designed to be a building block for a polychronous spiking neural network. The axonal delay can be programmed by presenting an input spike followed by a post-synaptic spike at the desired delay. An analogue memory was used to store this value. We also use spike timing dependent delay plasticity (STDDP) to reduce the errors in delay that result from the delay programming step. Measurements show that the proposed circuit is capable of learning and retaining delays in the range of 2 ms to 50 ms for many minutes.

Recent work in neuroscience is revealing how the blowfly rapidly detects orientation using neural circuits distributed directly behind its photo receptors. These circuits like all biological systems rely on timing, competition, feedback, and energy optimization. The recent realization of the passive memristor device, the so-called fourth fundamental passive element of circuit theory, assists with making low power biologically inspired parallel analog computation achievable. Building on these developments, we present a memristor-based neuromorphic competitive control (mNCC) circuit, which utilizes a single sensor and can control the output of N actuators delivering optimal scalable performance, and immunity from device variation and environmental noise.

We present a digital phase interpolator (PI) design for 65nm CMOS that avoids conventional analog structures, accurately achieves 2-bits phase resolution across a range of rise time and input delays from trise: 48ps → 200ps using a ratio trise/tdelayof at least 1 or greater. Increased accuracy is available for certain rise times using ratios increasing between 1 and 10 as verified by simulations across process corners using extracted parasitic capacitances but ignoring MOSFET mismatch effects. Power consumption was estimated at 30nW/MHz → 38nW/MHz across a range of process variation corners in these operating conditions. Monte Carlo simulations across process and MOSFET mismatch conditions show large variations in estimated accuracy. Monte Carlo trials show the PI achieves a worst case DNL error (mean±3σ) of 1.06 LSB using trise/tdelayratio of 5.3 and 48ps rise time, and a worst case DNL error (mean ±2σ) of 0.49 LSB for trise/tdelayratio of 4 and 84ps rise time.

In this paper we present the design and implementation of a low power neural amplifier which has two programmable gains in two programmable bandwidths. The bandwidths are programmable between 0.7-300Hz, suitable for measuring local field potentials and 1.95-5.4kHz, suitable for measuring action potentials. The amplifier achieves a maximum gain of 79dB in the higher bandwidth. A chip has been designed and implemented using a 0.5μm technology with 8 neural amplifiers. On average the neural amplifier consumes less than 14μW at 3.3V.

We present measurements from an aVLSI programmable axonal propagation delay circuit. It is intended to be used in the implementation of polychronous spiking neural networks. The delay can be programmed by presenting an input spike followed by a training spike at the desired delay. To fine tune and maintain the delay using an analogue memory, we use continuous spike timing dependent delay adaptation. Measurements presented here show that the axon circuit is capable of learning and retaining delays in the 2.5-20 ms range, as long as the neuron is stimulated at least once every few seconds.

The cross-correlation and auto-correlation operations are important in many signal processing tasks. Often these operations are resource intensive or limited by noise in low-power systems. In this paper we present the design and measured results of an analogue integrated circuit (IC) that performs cross-correlations using a neuromorphic algorithm.

There are a number of spiking and bursting neuron models with varying levels of complexity, ranging from the simple integrate-and-fire model to the more complex Hodgkin-Huxley model. The simpler models tend to be easily implemented in silicon but yet not biologically plausible. Conversely, the more complex models tend to occupy a large area although they are more biologically plausible. In this paper, we present the 0.5 μm complementary metal-oxide-semiconductor (CMOS) implementation of the Mihalaş-Niebur neuron model--a generalized model of the leaky integrate-and-fire neuron with adaptive threshold--that is able to produce most of the known spiking and bursting patterns that have been observed in biology. Our implementation modifies the original proposed model, making it more amenable to CMOS implementation and more biologically plausible. All but one of the spiking properties--tonic spiking, class 1 spiking, phasic spiking, hyperpolarized spiking, rebound spiking, spike frequency adaptation, accommodation, threshold variability, integrator and input bistability--are demonstrated in this model.

In this paper we present results from several implementations of silicon cochleae whose dynamics are governed by the Hopf equation. These silicon cochleae exhibit the majority of active, nonlinear characteristics of the biological cochlea such as large-signal compression, two-tone suppression, the creation of distortion products and so forth. Here we explore the coupling between resonant sections of the basilar membrane to investigate phenomena such as masking and the characteristic frequency response curve of the cochlea at a particular place along the basilar membrane. We see that the interaction of resonant sections can account for these phenomena and that we can use these observations to partially explain the connectivity of the afferent and efferent fibres to the outer hair cells. This work not only gives us valuable insight into the dynamical behaviour of the early auditory system but it also highlights the benefits of building circuits of these complex systems in order to produce models whose parameters can be tuned and whose outputs can be observed and measured in realtime.

We present an implementation of the Izhikevich neuron model which uses two first-order log-domain low-pass filters and two translinear multipliers. The neuron consists of a leaky-integrate-and-fire core, a slow adaptive state variable and quadratic positive feedback. Simulation results show that this neuron can emulate different spiking behaviours observed in biological neurons.

We present an electronic neuron that uses first-order log-domain low-pass filters to implement the Mihalas-Niebur model. The neuron consists of a leaky-integrate-and-fire core and building blocks to implement an adaptive threshold and spike induced currents. Simulation results show that this modular neuron can emulate different spiking behaviours observed in biological neurons.

We have designed, constructed and tested an electromechanical acoustic sensor as a conceptual model for the active process in the mammalian cochlea. The sensor is based on a mechanical resonator - a stretched latex band - which is tonically (tensionally) modulated by an electromechanical actuator. A feedback circuit senses the motion of the resonator, and modulates its tension at twice the frequency of its motion. An amplifier is thereby formed, which is self-tuned to the circuit's resonance, and which produces gain by regeneration and degenerate parametric pumping. The system is simple in structure; physiologically plausible as a model for the basilar membrane and associated hair cells; and reproduces several well-known features of the cochlear amplifier.

We describe an electromechanical acoustic sensor which we have constructed and tested as a conceptual model for the active process in the mammalian cochlea. The sensor is based on a mechanical resonator - a stretched latex band - which is tonically (tensionally) modulated by an electromechanical actuator. A feedback circuit senses the motion of the resonator, and modulates its tension at twice the frequency of its motion. An amplifier is thereby formed, which is self-tuned to the circuit's resonance, and which produces gain by regeneration and degenerate parametric pumping. We show that this system is surprisingly simple in structure; is physiologically plausible as a model for the basilar membrane and associated structures; and that it reproduces several well-known features of the cochlear amplifier, such as the variation in center frequency and bandwidth with gain, and a cubic transfer characteristic in open loop.

We implemented a Symbolic Circuit Analysis Software toolbox based on Affine Arithmetic. The toolbox is defined with small signal Affine MOSFET models along with conventional MOSFET models. As a case study the demonstration compares the use of affine models with conventional models in various circuit architectures. The symbolic analysis results are also compared with SPICE analysis results. This demonstration is associated with CAD and other tools for Analog Design track (Track 1.12).

In this paper we present the circuits and simulation results for a silicon neuron which is based on a modified version of the Mihalas-Niebur neural model [1]. This silicon neuron produces 15 of the 20 known neural spiking and bursting behaviors. It has low complexity and reliable matching and can thus be easily integrated into more complex neuromorphic systems. Implemented in a 0.15um 1.5V CMOS process, each neuron consumes about 7.5nW of power at 1kHz and occupies an area of 70um by 70um.

In this paper we present a 2-D silicon cochlea which includes an automatic quality factor control (AQC) loop. This control-loop is an improved version of that presented in [1] where the control-loop imposes both a ceiling and a threshold level on the output amplitude of the basilar membrane (BM) resonators. In this improved version we include only a single set-point in our control-loop. This allows us to tune the BM resonators close to a Hopf bifurcation. We present test results from a fabricated integrated circuit which, when compared with biological data, demonstrates the feasibility of our active 2-D cochlea model.

Recent work in cochlear amplifier modeling has focused on systems which show the dynamics of a Hopf bifurcation. We show that these systems are examples of a generic amplifier topology, the self-tuned regenerative amplifier (STRA). The STRA is a feedback-stabilized regenerative amplifier that can be operated in a region of supercritical stability. The signatures of Hopf amplification, such as a cubic nonlinear small-signal response at resonance, are general features of the topology. The topology is shown to include a degenerate parametric amplifier, which may explain its low noise and insensitivity to input-feedback phase mismatch.

In this paper we present a basilar membrane resonator design for an active 2D cochlea. It incorporates some of the non-linear behaviour exhibited in the real cochlea by utilizing a quality factor control loop. This control loop varies the gain and the frequency selectivity of the resonator based on the amplitude of the input signal.

Using various layout techniques and circuit configurations, the effects of matching on a log-domain filter were analyzed. It is shown here that one of three possible Tau cell configurations to implement the same 2nd order low pass filter clearly outperforms the others. Furthermore, application of a common centroid layout technique has had no noticeable improvement on filter matching

Female crickets can locate males by phonotaxis to the mating song they produce. The behaviour and underlying physiology has been studied in some depth showing that the cricket auditory system solves this complex problem in a unique manner. We present an analogue very large scale integrated (aVLSI) circuit model of this process and show that results from testing the circuit agree with simulation and what is known from the behaviour and physiology of the cricket auditory system. The aVLSI circuitry is now being extended to use on a robot along with previously modelled neural circuitry to better understand the complete sensorimotor pathway. 1 In t r o d u c t i o n Understanding how insects carry out complex sensorimotor tasks can help in the design of simple sensory and robotic systems. Often insect sensors have evolved into intricate filters matched to extract highly specific data from the environment which solves a particular problem directly with little or no need for further processing [1]. Examples include head stabilisation in the fly, which uses vision amongst other senses to estimate self-rotation and thus to stabilise its head in flight, and phonotaxis in the cricket. Because of the narrowness of the cricket body (only a few millimetres), the Interaural Time Difference (ITD) for sounds arriving at the two sides of the head is very small (1020s). Even with the tympanal membranes (eardrums) located, as they are, on the forelegs of the cricket, the ITD only reaches about 40s, which is too low to detect directly from timings of neural spikes. Because the wavelength of the cricket calling song is significantly greater than the width of the cricket body the Interaural Intensity Difference (IID) is also very low. In the absence of ITD or IID information, the cricket uses phase to determine direction. This is possible because the male cricket produces an almost pure tone for its calling song. * + School of Electrical and Information Engineering, Institute of Perception, Action and Behaviour. Figure 1: The cricket auditory system. Four acoustic inputs channel sounds directly or through tracheal tubes onto two tympanal membranes. Sound from contralateral inputs has to pass a (double) central membrane (the medial septum), inducing a phase delay and reduction in gain. The sound transmission from the contralateral tympanum is very weak, making each eardrum effectively a 3 input system. The physics of the cricket auditory system is well understood [2]; the system (see Figure 1) uses a pair of sound receivers with four acoustic inputs, two on the forelegs, which are the external surfaces of the tympana, and two on the body, the prothoracic or acoustic spiracles [3]. The connecting tracheal tubes are such that interference occurs as sounds travel inside the cricket, producing a directional response at the tympana to frequencies near to that of the calling song. The amplitude of vibration of the tympana, and hence the firing rate of the auditory afferent neurons attached to them, vary as a sound source is moved around the cricket and the sounds from the different inputs move in and out of phase. The outputs of the two tympana match when the sound is straight ahead, and the inputs are bilaterally symmetric with respect to the sound source. However, when sound at the calling song frequency is off-centre the phase of signals on the closer side comes better into alignment, and the signal increases on that side, and conversely decreases on the other. It is that crossover of tympanal vibration amplitudes which allows the cricket to track a sound source (see Figure 6 for example). A simplified version of the auditory system using only two acoustic inputs was implemented in hardware [4], and a simple 8-neuron network was all that was required to then direct a robot to carry out phonotaxis towards a species-specific calling song [5]. A simple simulator was also created to model the behaviour of the auditory system of Figure 1 at different frequencies [6]. Data from Michelsen et al. [2] (Figures 5 and 6) were digitised, and used together with average and "typical" values from the paper to choose gains and delays for the simulation. Figure 2 shows the model of the internal auditory system of the cricket from sound arriving at the acoustic inputs through to transmission down auditory receptor fibres. The simulator implements this model up to the summing of the delayed inputs, as well as modelling the external sound transmission. Results from the simulator were used to check the directionality of the system at different frequencies, and to gain a better understanding of its response. It was impractical to check the effect of leg movements or of complex sounds in the simulator due to the necessity of simulating the sound production and transmission. An aVLSI chip was designed to implement the same model, both allowing more complex experiments, such as leg movements to be run, and experiments to be run in the real world. Figure 2: A model of the auditory system of the cricket, used to build the simulator and the aVLSI implementation (shown in boxes). These experiments with the simulator and the circuits are being published in [6] and the reader is referred to those papers for more details. In the present paper we present the details of the circuits used for the aVLSI implementation.