High speed architectures usually employ some form of parallelism or concurrency. Parallel or concurrent execution of a program not only increases the rate at which references are issued to the memory system but also changes the behavior of these references, relative to its serial-scalar execution. This paper reports the variations in program memory reference behavior when automatically transformed by a compiler and executed on parallel and vector archirectures. Using traces of the PERFECT benchmark set, executed on on Aliiant FX180 in a single scalar processor, single vector processor, scalar multiprocessor and vector multiprocessor modes, measurements are reported for issue rates, reference locality and data sharing.

This paper reports the cache performance of a set of vectorized numerical program from the Perfect Club benchmarks. Using a low cost trace driven simularion technique we show how a non-prefetching vector cache can result in unpredictable performance and how rhis unpredictability makes it difficult to find a good block size. We describe two simple prefetch schemes to reduce the influence of long stride vector accesses and misses due IO block invalidations in mulliprocessor vector caches. These two schemes are shown to have better performance than a non-prefetching cache.