Demo Data from EDBT 2026 / reviewers in the wild / expert
Gunes Aybay
dblp:84/6796
· DBLP profile ↗
5ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 77% Electronic design automation · 23% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › cache coherence › cache coherence protocol
cache coherence protocol verification |
0.0 | 1 | 1998 | Design Verification of the S3.mp Cache-Coherent Shared-Memory System · IEEE Trans. Computers 1998 |
Memory systems › memory consistency
memory consistency verification |
0.0 | 1 | 1998 | Design Verification of the S3.mp Cache-Coherent Shared-Memory System · IEEE Trans. Computers 1998 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1998 | Design Verification of the S3.mp Cache-Coherent Shared-Memory System · IEEE Trans. Computers 1998 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1998 | Design Verification of the S3.mp Cache-Coherent Shared-Memory System · IEEE Trans. Computers 1998 |
Methods — techniques the papers use, named apart from their topics
abstraction-level verification · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | Design Verification of the S3.mp Cache-Coherent Shared-Memory SystemabstractThis paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable Shared-memory MultiProcessor (S3.mp) at three levels of abstraction: the memory consistency model, the cache coherence protocol, and the implementation. Fong Pong, Michael C. Browne, Gunes Aybay, Andreas Nowatzyk, Michel Dubois 0001 |
IEEE Trans. Computers | 3 |
| 1995 | Exploiting Parallelism in Cache Coherency Protocol Engines
Andreas Nowatzyk, Gunes Aybay, Michael C. Browne, Edmund J. Kelly, Michael Parkin, Bill Radke, Sanjay Vishin |
Euro-Par | 2 |
| 1995 | Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study
Fong Pong, Andreas Nowatzyk, Gunes Aybay, Michel Dubois 0001 |
Euro-Par | 3 |
| 1995 | The S3.mp Scalable Shared Memory Multiprocessor
Andreas Nowatzyk, Gunes Aybay, Michael C. Browne, Edmund J. Kelly, Michael Parkin, Bill Radke, Sanjay Vishin |
ICPP (1) | 2 |
| 1993 | The S3.mp Architecture: A Local Area MultiprocessorabstractNo abstract available. Andreas Nowatzyk, M. Monger, Michael Parkin, Edmund J. Kelly, Michael C. Browne, Gunes Aybay |
SPAA | 6 |