This paper presents a 2-stage pipelined-SAR ADC with artificial-neural-network (ANN) based digital calibration algorithm to calibrate the mismatch error in the$1^{\mathrm {st}}$-stage capacitive DAC (CDAC) and the inter-stage gain error (IGE) together. Previous ANN-based calibration schemes suffer from excessive power and hardware overhead due to the large number of network parameters. To facilitate hardware implementation, the proposed algorithm only requires$N_{1}+1$input parameters ($N_{1}$is the resolution of the$1^{\mathrm {st}}$-stage SAR ADC), in which the overall output of the$2^{\mathrm {nd}}$-stage SAR ADC is combined into a single parameter. In addition, the ANN utilizes a single-neuron hidden layer with linear activation function to calculate the actual bit weight of the ADC, remarkably reducing the hardware overhead and power consumption of the calibration circuit. The prototype 12-bit, 250 MS/s pipelined-SAR ADC with “loop-unrolled” architecture is implemented in 40-nm CMOS, in which a ring amplifier with improved bias circuit is used to realize a robust closed-loop gain for residue amplification. With the ANN-based calibration circuit implemented in an FPGA, the calibrated ADC achieves the SNDR of 65.0 dB and the SFDR of 84.0 dB at Nyquist input (124 MHz), with a Schreier figure of merit of 169.0 dB and a Walden figure of merit of 14.0 fJ/conv-step. The ADC core consumes 4.95 mW, with an active area of only 0.013 mm2.

This article presents a 1st-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a hybrid error-feedback (EF) and cascaded-integrator-feed-forward (CIFF) structure assisted by a unity-gain buffer (UGB). Without using a multi-input comparator which is widely adopted in conventional 1st-order passive NS structures, the proposed hybrid EF-CIFF structure realizes a more ideal 1st-order noise transfer function (NTF) with a reasonable capacitance ratio, so as to obtain better NS effect. Fabricated in a 28-nm CMOS technology, the prototype NS-SAR ADC consumes 150$\mu \text{W}$under a 0.9-V supply voltage when operating at 40-MS/s sampling rate. A 75-dB signal-to-noise-and-distortion ratio (SNDR) is measured for a 2.47-MHz sinusoid input under an oversampling ratio (OSR) of 8. It achieves a peak Schreier figure-of-merit (FoM) of 177.2 dB and the core circuit occupies 0.012-mm2 area.

This paper presents an improved 1st-order fully passive noise-shaping (NS) scheme for NS SAR ADCs. In order to move the zero and pole of the noise transfer function (NTF) closer to the unit circle, a structure combining charge pump and two-input comparator is used to provide two gain factors of 2 and 3, respectively, forming an NTF with zero and pole located at (0.875, 0) and (-0.75, 0), respectively. The improved NTF can provide better noise suppression effect than conventional NTFs. To ensure the stability of the ADC, a gain calibration technique is proposed for the two-input comparator to ensure the gain ratio between the 2 input branches, which can prevent the pole from moving outside the unit circle because of the gain mismatch between the comparator's 2 input branches. In addition, the proposed structure can merge the integration cycle into the sampling phase to enhance the conversion speed. Based on the proposed idea, an NS SAR ADC with a 10-bit DAC is designed in 65-nm CMOS, with post-layout simulation results showing that a 76-dB SNDR is achieved with 2.5-MHz signal bandwidth and 40-MS/s sampling rate.