An approximate upper bound is derived to the maximum likelihood decoding threshold of weighted nonbinary repeat-accumulate (WNRA) codes over GF(q) with q-ary orthogonal modulation and coherent detection over the additive white Gaussian noise channel. As with binary RA codes, WNRA codes show the potential for achieving the channel capacity with decreasing code rate for large enough q.

Using a Gaussian approximation to the distribution of the message vectors under density evolution, we design irregular weighted nonbinary repeat-accumulate codes over GF(q) with q-ary orthogonal modulation. The resulting codes achieve a frame error rate of 10-1within 0.56 to 0.91 dB of channel capacity under the AWGN channel.

A very simple design rule for parallel concatenated Turbo codes over GF(q) with q-ary orthogonal modulation is proposed. Unlike previously proposed exhaustive search methods, the proposed design rule allows straightforward and systematic code designs for any value of q ≥ 2 and any constraint length greater than 2.

In this paper, a distribution matching technique is proposed to process the extrinsic information produced by practical multiple-antenna detectors with iteratively demodulated, bit-interleaved coded modulation (BICM-ID). It is shown that significant gains may be achieved by appropriately processing the extrinsic information generated by practical multiple-antenna detectors before feeding it to the channel decoder. The validity of the proposed matching technique is shown via simulation results applied to Turbo-coded BICM-ID systems using (QRD)-M and list sphere detectors.

A low energy modulo-multiplier is proposed for elliptic curve cryptography (ECC) processor, especially for authentication in mobile device or key encryption in embedded health-care system. The multiplier uses only two 40-bit multipliers to execute 160-bit operation based on the Montgomery modulo-multiplication algorithm. Partial products of multiplication are accumulated with shift registers to get final 160-bit MSB of output value. One modulo-multiplication is executed with 20 clock cycles at 40MHz operating frequency. It consumes 6.3nJ for each modulo-multiplication at 1V supply voltage. It is implemented by using 0.18-μm CMOS process and has 0.7mm × 1.0mm area.