The Bulk-Synchronous Parallel (BSP) model was proposed by Valiant as a standard interface between parallel software and hardware. In theory, the BSP model has been shown to allow the asymptotically optimal execution of architecture independent software on a variety of architectures. Our goal in this work is to experimentally examine the practical use of the BSP model on current parallel architectures. We describe the design and implementation of the Green BSP Library, a small library of functions that implement the BSP model, and of several applications that were written for this library. We then discuss the performance of the library and application programs on several parallel architectures. Our results are positive in that we demonstrate efficiency and portability over a range of parallel architectures and show that the BSP cost model is useful for predicting performance trends and estimating execution times.

BSPlib is a small communications library for bulk synchronous parallel (BSP) programming which consists of only 20 basic operations. This paper presents the full definition of BSPlib in C, motivates the design of its basic operations, and gives examples of their use. The library enables programming in two distinct styles: direct remote memory access (DRMA) using put or get operations, and bulk synchronous message passing (BSMP). Currently, implementations of BSPlib exist for a variety of modern architectures, including massively parallel computers with distributed memory, shared memory multiprocessors, and networks of workstations. BSPlib has been used in several scientific and industrial applications; this paper briefly describes applications in benchmarking, Fast Fourier Transforms (FFTs), sorting, and molecular dynamics.

Article Towards efficiency and portability: programming with the BSP model Share on Authors: Mark Goudreau Department of Computer Science, University of Central Florida, Orlando, FL Department of Computer Science, University of Central Florida, Orlando, FLView Profile , Kevin Lang NEC Research Institute, 4 Independence Way, Princeton, NJ NEC Research Institute, 4 Independence Way, Princeton, NJView Profile , Satish Rao NEC Research Institute, 4 Independence Way, Princeton, NJ and University of California at Berkeley, Berkeley, CA NEC Research Institute, 4 Independence Way, Princeton, NJ and University of California at Berkeley, Berkeley, CAView Profile , Torsten Suel NEC Research Institute, 4 Independence Way, Princeton, NJ and University of California at Berkeley, Berkeley, CA NEC Research Institute, 4 Independence Way, Princeton, NJ and University of California at Berkeley, Berkeley, CAView Profile , Thanasis Tsantilas Department of Computer Science, Columbia University, New York, NY Department of Computer Science, Columbia University, New York, NYView Profile Authors Info & Claims SPAA '96: Proceedings of the eighth annual ACM symposium on Parallel Algorithms and ArchitecturesJune 1996 Pages 1–12https://doi.org/10.1145/237502.237503Online:24 June 1996Publication History 45citation447DownloadsMetricsTotal Citations45Total Downloads447Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We study the problem of interprocessor communication in a parallel computer model suggested by recent Their algorithm is complicated as opposed to ours that we believe to be practical.Optimal interprocessor communication algorithms in realistic models of parallel computers are not only interesting in their own sake, they are one of the main components in optimally simulating PRAMs as well aa implementing Valiant's bulk-synchronous parallel model [13, 19, 18].

we show that sorting an input of size N = n2 can be performed by an n x n mesh-connected processor array in 2.5n + o(n) parallel communication steps and using constant size queues, with high probability.The best previously known algorithm for this problem required 37L + o(n) steps.We also show that selecting the element of rank k out of N = n2 inputs on an n x n mesh can be performed in 1.25n + o(n) steps and using constant size queues, with high probability.The best previously known algorithm for this problem involved sorting, and required 3n + o(n) steps.Both of our algorithms can be generalized to higher dimensions, achieving bounds better than the known results.

Article Free Access Share on Tight bounds for oblivious routing in the hypercube Authors: C. Kaklamanis Aiken Computation Laboratory, Harvard University, Cambridge, MA Aiken Computation Laboratory, Harvard University, Cambridge, MAView Profile , D. Krizanc Department of Computer Science, University of Rochester, Rochester, NY Department of Computer Science, University of Rochester, Rochester, NYView Profile , T. Tsantilas Aiken Computation Laboratory, Harvard University, Cambridge, MA Aiken Computation Laboratory, Harvard University, Cambridge, MAView Profile Authors Info & Claims SPAA '90: Proceedings of the second annual ACM symposium on Parallel algorithms and architecturesMay 1990 Pages 31–36https://doi.org/10.1145/97444.97453Published:01 May 1990Publication History 57citation682DownloadsMetricsTotal Citations57Total Downloads682Last 12 Months63Last 6 weeks8 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF