The increasing complexity of safety-critical hardware systems demands advanced methods for ensuring functional safety (FuSa). Traditional techniques like ATPG and BIST are intrusive, requiring additional hardware and disrupting operations, making them unsuitable for in-field testing. To address this, for the first time, we propose a machine learning (ML)-driven automated Self-Test Library (STL) generation for seamless in-field testing during idle periods, ensuring uninterrupted fault detection and high system performance. Utilizing reinforcement learning, the STL generates design-specific test patterns, achieving up to $57.57 \%$ improvement in fault coverage and up to $85 \%$ efficiency compared to existing pattern-based testing, enhancing FuSa in mission-critical applications.

The increasing complexity of Electrical and Electronic (E/E) systems underscores the need for protective measures to ensure functional safety (FuSa) in high-assurance environments. This entails the identification and fortification of vulnerable nodes to enhance system reliability during mission-critical scenarios. Traditionally, the assessment of E/E system reliability has relied on fault injection (FI) techniques and simulations. However, FI faces challenges in coping with escalating design complexity, including resource demands and timing overheads. Furthermore, it falls short in identifying critical components that may lead to functional failures. To address these challenges, we propose a Machine Learning (ML)-based framework for predicting critical nodes in hardware designs. The process begins with constructing a graph from the design netlist, forming the foundation for training a Graph Convolutional Network (GCN). The GCN model utilizes graph node attributes, node labels, and edge connections to learn and predict critical nodes in the circuit. The model furnishes up to 93.7% accuracy in identifying vulnerable circuit nodes during evaluation on diverse designs such as Synchronous Dynamic Random Access Memory (SDRAM) controller, OpenRISC 1200 (OR1200) modules. Furthermore, we incorporate an explainability analysis to interpret individual node predictions. This analysis discerns the critical design factors influencing fault criticality in the design. Moreover, to the best of our knowledge, we, for the first time, perform a regression analysis to generate node criticality scores, quantifying the degrees of criticality, that can enable prioritizing resources towards critical nodes.

As the use of safety critical systems is becoming more prevalent, there is a need to reduce the implementation overhead required to provide safety. The conventional design of such systems does not consider application behaviours, thereby resulting in a pessimistic design where the safety provided is often not required during large periods of the application execution. In this paper, we analyse the different phases of an application during its overall execution life cycle, together with the embedded threads to perform specific operations, and propose a new methodology for protection of the safety critical application threads. We show the benefits of this method and the ability to build lower cost systems which are functionally safe using the flexibility which is embedded inside the application itself. Two new application based protection schemes, based on altering the application execution parameters (e.g. control loop frequency) and redundant execution of selective threads, are proposed. For these experiments, we have used commercial off the shelf components without any hardware functional safety features and implemented safety measures by augmenting the application software. Experiments on Electric Vehicle Traction (EVT) and On-Board Charger (OBC) applications indicate overall MIPS savings between 70% to 95%. These results indicate that a careful design of the application can itself be the first step to protect the integrated circuits which drive them.

Model Predictive control is a modern method of nonlinear control which gives superior performance with the cost of increased computational burden. In this paper, continuous control set model predictive control (CCS-MPC) for buck converter is proposed. This control strategy achieves constant switching frequency and retains the advantage of faster response of Model predictive control(MPC). The proposed algorithm is based on sampled data model of buck converter. The computation related to solution of a continuous optimization problem is done through a polynomial approximation of a transcendental function. The paper also shows how this approximation is valid for all practically designed buck converters. The proposed control strategy is verified in simulation and compared with experimental results, and it shows good performance for both reference tracking and disturbance rejection. It is superior compared to classical PI with lead controller and is about six times faster than conventional PI with lead controller.

Advances in both semiconductor and automotive industry are today enabling the next generation of vehicles with significant electronics content than ever before. Consumers can now avail vehicle offerings in the form of Electric and Hybrid Electric Vehicles (EV/HEV) that have improved fuel efficiency, provide enhanced driver-passenger comfort and experience through Advance Driver Assistance Systems (ADAS) and car infotainment systems, and more. Increasing electronics, software content, and connectivity drive two consumer concerns - “functional safety” and “security” - to the forefront. In this tutorial, we dissect these concerns from an end application perspective and translate the system level requirements and standards into semiconductor development requirements. We indicate both current and emerging practices, and touch upon areas requiring new or optimal design and electronic design automation (EDA) solutions. While functional safety is the primary focus for deep-dive in this tutorial, we also examine key facets of automotive security which is now emerging as a critical area for further understanding and standardization.

Many real-life systems have integrated circuits interacting with physical systems in safety critical applications. These systems are called hybrid systems. The safety analysis of integrated circuits used in such systems is typically done in isolation of the end application and associated physical system, and hence results in the need to take recourse to conservative design techniques utilizing costly redundancy. We are gradually moving away from the paradigm of independently designing the digital and physical parts of hybrid systems towards simultaneous considerations for both. These systems have an acceptable tolerance determined by the application due to the inertial nature of the physical system, error tolerance capability in closed loop applications, built-in hardware and software functionality, etc. In this paper, we perform a comparative study of integrated circuit safety analysis as practiced today and system level application specific safety analysis that incorporates a physical system. We propose an improved method based upon the divide and conquer approach for such co-analysis to address practical limitations associated with adopting system level analysis techniques during integrated circuit design. Experimental results for a representative motor control system indicate that the application has an error tolerance of 92–160 cycles of closed loop operation for worst case errors and a control value error tolerance in the range of 5–7% at different operating conditions. Incorporation of application tolerance results in up to 4.3X reduction in the number of hardware elements which need to be protected.

Integrated circuits are being used in different applications which are not always known at the time of specification and design creation. Safety standards specify that certain design processes be followed to guarantee safety of the applications in which these circuits are being used. As a result, the design phase is followed (often mandated) by an evaluation phase, wherein the safety worthiness of the circuit must be ascertained. In this paper, we perform a detailed study of such an evaluation as practised in the industry, understand the limitations, and propose techniques to improve the existing methodology. The improvements proposed are: (i) Capturing workload diversity as input constraints (values and sequence). (ii) Modelling application specific performance tolerance. (iii) Illustrating how physical system can be included into this analysis using a suitable representation. (iv) Budgeting of tolerance across various interacting modules to reduce computational complexity of safety analysis. Experimental results to illustrate suitability of the proposed methods are presented using a set of ITC benchmark circuits and two representative industrial circuits.

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e.g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

Soft errors are one of the biggest reliability challenges for present day electronic devices. With technology scaling, the contribution of soft errors to overall device failure is on the rise and it is becoming the dominant reliability failure mechanism. Several techniques exist for the detection and correction of soft errors. Reducing implementation overhead is one of the areas which researchers were focusing on, and several optimization techniques are being proposed. In this paper, we propose a novel methodology, using error detection and correction codes to reduce the implementation overhead. We extend the earlier work on delayed capture methodology, and divide the total number of flip-flops into various groups and calculate the check bits for each group. This method exploits the reduction in the fault space which is generated due to single event upsets, and illustrates how the detection and correction implementation overheads can be minimized. Experimental results highlight the effectiveness of this technique. As compared to the original implementation, 44.80% reduction in area is obtained, without sacrificing the coverage.

With the scaling of technology node and voltage levels, the susceptibility of logic to soft errors is increasing. Hence it is very important to take care of soft errors in the combinational logic along with those in the sequential elements. In this paper, a novel method is proposed to detect the presence of soft errors in both combinational and sequential logic. In this method, flip-flops are grouped and parity is computed for each group twice - once at the input of the flip-flops and next at the output. Later, the parity at the inputs and outputs is compared to detect the presence of soft errors. The effectiveness of the technique is shown through experimental results.

Automotive electronics today is characterased by two requirements. One is the well-known aspect of reliability of the components used to build the system. The other is the increasing need for commoditisation of these systems. These requirements pose the dual challenges of meeting very strict quality goals, while at the same time also adhering to affordable cost goals. Devices designed for one end application often find use in others. Consequently, it is important that these devices be designed and tested in a scaleable manner, wherein the high quality and low cost goals are simultaneously met. In this paper, a case study is presented on a set of recently designed automotive chips at Texas Instruments (India). Illustrations of different techniques are given, together with supporting data. These techniques are generic enough to be adopted and further improvised to enhance test cost and test quality optimisations in a larger class of SOCs as well.