Ruihan Chen, Qiming Li, Xiaocheng Feng, Weihong Zhong, Xiaoliang Yang, Yuxuan Gu, Zekun Zhou, Yunfei Lu, Haoyu Ren, Kun Chen, Dandan Tu, Bing Qin. Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers). 2026.

Generative diffusion models have received increasing attention in medical imaging, particularly in limited-angle computed tomography (LACT). Standard diffusion models achieve high-quality image reconstruction but require a large number of sampling steps during inference, imposing a heavy computational burden. Although skip-sampling strategies have been proposed to improve efficiency, they often lead to loss of fine structural details. To address this issue, we propose a Prior-aware Wavelet Diffusion for Efficient Dental Limited-angle CT Reconstruction (PWD). The PWD enables efficient sampling while preserving reconstruction fidelity in LACT, and effectively mitigates the degradation typically introduced by skip-sampling. Specifically, during the training phase, PWD maps the distribution of LACT images to that of fully sampled target images, enabling the model to learn structural correspondences between them. During inference, the LACT image serves as an prior-aware to guide the sampling trajectory, allowing for high-quality reconstruction with significantly fewer steps. In addition, PWD performs multi-scale feature fusion in the wavelet domain, effectively enhancing the reconstruction of fine details by leveraging both low-frequency and high-frequency information. Quantitative and qualitative evaluations on clinical dental arch CBCT and periapical datasets demonstrate that PWD outperforms existing methods under the same sampling condition. Using only 50 sampling steps, PWD achieves at least 1.7 dB improvement in PSNR and 10% gain in SSIM.

A fully-integrated half-bridge driver with dual N-type power transistors is proposed in this paper, which adopts on-chip charge pumps with integrated capacitors based on charge sharing to avoid external bootstrap components. Without bootstrap-capacitor charging paths through low-side power transistors and high-frequency high-power switching nodes, overcharge and large electro-magnetic interference (EMI) can be avoided by eliminating parasitic interconnect inductance and body diode. Adaptive dead time is employed to enhance efficiency, enabling the system to achieve appropriate dead times in various applications. Besides, 100% duty-cycle control is realized by duty-cycle detection and additional continuous charge pump, which can charge the on-chip driver capacitor during on-time, the restriction of minimum off-time is eliminated and the proposed driver can work at full duty cycle range. The proposed charge-sharing-based (CSB) half-bridge driver with any duty-cycle capability embedded in a buck converter with 2A load is implemented in a 0.18 μm BCD technology, which occupies an active area of 0.151mm2. Verification results demonstrate that a 2.2 MHz switching frequency is realized with 2.4V–5.5V input voltage and a peak efficiency of 96.8% is achieved for 5 to 4V conversion. The minimum regulation voltage difference between input voltage and output voltage is 70 mV with the help of 100% duty-cycle circuit.

We present an novel framework for efficiently and effectively extending the powerful continuous diffusion processes to discrete modeling. Previous approaches have suffered from the discrepancy between discrete data and continuous modeling. Our study reveals that the absence of guidance from discrete boundaries in learning probability contours is one of the main reasons. To address this issue, we propose a two-step forward process that first estimates the boundary as a prior distribution and then rescales the forward trajectory to construct a boundary conditional diffusion model. The reverse process is proportionally adjusted to guarantee that the learned contours yield more precise discrete data. Experimental results indicate that our approach achieves strong performance in both language modeling and discrete image generation tasks. In language modeling, our approach surpasses previous state-of-the-art continuous diffusion language models in three translation tasks and a summarization task, while also demonstrating competitive performance compared to auto-regressive transformers. Moreover, our method achieves comparable results to continuous diffusion models when using discrete ordinal pixels and establishes a new state-of-the-art for categorical image generation on the Cifar-10 dataset.

In this article, a monolithic gallium nitride (GaN)-based half-bridge power stage is proposed for high frequency power converter. A level shifting technique with buffering device and shielding capacitance is designed to perform communications in half-bridge topologies with high reliability and low propagation delay. To prevent the missing pulse or output latch during deadtime, a negative voltage pull-down circuit is designed. Implemented with a$0.25\mu \mathrm{m}$15-V enhanced mode GaN (eGaN) process, this work consists of optimized delay matching, monolithic gate drivers and power high electron mobility transistors(HEMTs) as well. The implementation results show that this work can achieve a propagation delay of no more than 6.5ns, a delay mismatch within 2.5ns and a CMTI capability above 150V/ns at 30Mhz switching frequency.

In HV (high-voltage) and HF (high-frequency) applications, SiC (silicon carbide) MOSFET is widely used for its small parasitic characteristics and fast switching speed. Using discrete devices on PCB, the active gate driver is usually adopted to restrict EMI (electromagnetic interference) noise. This method could achieve a limited switching performance improvement, and many disadvantages still exist. In this paper, the integrated adaptive multi-level gate driver is presented to improve the switching performance of SiC MOSFET in HV and HF applications. The proposed gate driver is realized on the chip using critical techniques such as dV/dt noise attenuation, high-speed circuit, and anti-false triggering mechanism. Then, the proposed gate drive is fabricated in a$0.18~\mu \text{m}$BCD process and occupies a 4.16 mm2 active area. The experimental results show that SiC MOSFET can achieve a 200 ns switching time, 0.8 mJ energy losses, no more than 15 V/ns average dV/dt noises, and 1.5 A/ns average di/dt noises under a 600 V power supply and a 33 A load. SiC MOSFET can also realize the excellent switching performance at different load currents from 15 A to 90 A by using the proposed adaptive multi-level gate driver.

The primary-side regulation (PSR) flyback converters with the feature of constant current (CC) and constant voltage (CV) are widely used in charger systems and adaptors of electronic devices. However, the conventional method of CC control is complex and inaccuracy, and more circuits should be added to improve accuracy causing more complex design and larger cost. In this paper, a novel strategy of CC control strategy based on large signal control is proposed to achieve simple and high-precision CC control which operates seamlessly as working state switched between CC and CV. The control chip is implemented in a 0.18μm BCD process, and the deviation of output current in CC mode is less than ± 2% without loop compensation. It well meets the demand of large charging current in startup and limiting current under low voltage condition.

To satisfy fast and high dV/dt immunity driver for wide-bandgap power device applications, speed and dV/dt immunity of the conventional level shifter should be improved. In this paper, a sub-nanosecond level shifter has been proposed, which has ultra-high dV/dt immunity without any additional circuit. Using the edge detection technique, the propagation delay of the proposed level shifter has been reduced significantly. The proposed level shifter is established in a 0.5 μm and a 0.18 μm BCD processes, whose results demonstrate a 520ps propagation delay with the 0.5μm process and a 170ps propagation delay with the 0.18μm process are realized, respectively. More than 250V/ns dV/dt immunity is achieved, which only occupies a 0.022mm2active area with the 0.5μm BCD process.

In high switching frequency applications, for the purpose of the high efficiency and low electromagnetic interference (EMI), an adaptive soft switching technique is proposed in this paper. According to the resonance characteristics of system, a valley point detection circuit is designed. Besides, considering the driving delay of power MOSFET, an adaptive control circuit is proposed to generate a flag signal of driver, by which the adaptive zero voltage switching (AZVS) can be achieved. With the help of proposed AZVS, the precise zero voltage switching independent of driving delay and type of power MOSFET can be automatically realized. An AZVS control circuit is implemented in a 0.35μm BCD process. It allows high efficiency and low EMI, as well as good thermal performance.

In this paper, a MOSFET-only voltage reference with novel curvature-compensation is proposed. In order to reduce the temperature coefficient in the proposed voltage reference, two proportional to absolute temperature voltages with opposite second-order order TC are added on a threshold voltage, which is achieved by a resistorless threshold voltage extractor. Besides, self-biased current source with feedback is realized at the same time, which can provide bias current for the whole voltage reference and enhance the performance of generated voltage reference without additional power consumption. Verification results of the proposed voltage reference implemented with 0.35µm technology process show that the temperature coefficient is 2.4 ppm/□ with a temperature range of −20□ to 80□ is obtained, and a 62.9 dB power supply rejection ratio is achieved with a 68nA maximum supply current.

This paper presents a voltage reference (VR) with a power supply rejection (PSR) better than 50 dB for frequencies of up to 60 MHz, and uses MOSFETs in strong inversion. Another innovation is a compact MOSFET low-pass filter, which was developed along with a feedback technique for a wide-bandwidth PSR not achieved in previous works. The proposed all-MOSFET VR was fabricated using a standard 0.18 μm CMOS process. It achieves a minimum temperature coefficient of 6.5 ppm/°C for temperatures from -30 °C to 110 °C. The line regulation is 0.076%/V for a step from 0.8 to 2.2 V supply voltage with 360 nW power consumption at room temperature and an area of 0.0143 mm2.

A current-efficent, fully integrated low-dropout regulator(LDO) with improved load transient responses for system-on-chips(SoC) is presented in this paper. It makes use of high bandwidth common-gate amplifier and slew-rate enhancement circuit(SRE) triggered by voltage spikes to improve output voltage spike and response time of the LDO greatly. The proposed circuit has been implemented in a 0.35μm standard CMOS process and occupies an active chip area of 0.057mm2. Experimental results show that it can deliver 100mA load current at 150mV dropout voltage. It only consumes 8μA quiescent current and is able to recover within 0.2μs even under the maximum load current change. Consequently, a low-power and ultra-fast capacitor-less LDO can be achieved.

A voltage mode power converter with the function of digitally duty cycle tuning is presented. Enough loop gain is required to guarantee a good load regulation. In the proposed design, the load regulation can be improved through digitally duty cycle tuning, based on phase lead compensated voltage mode power converters. The whole circuit is implemented in a 0.13μm 1P8M CMOS process. The simulation results show that the output voltage's deviation can be controlled within ±10mV when the load current steps from 200mA to 1.65A, and a 14μV/mA load regulation can be obtained.