As CMOS technology scales down, the number of standard cells increases rapidly. The increasing cell count raises the complexity of physical design. Routing is one of the most time-consuming stages in the physical design flow. When routing fails to meet design rules or performance targets, designers must revise earlier stages such as floorplanning or placement. Repeating the routing process causes high design cost and long time-to-market. Early prediction of routing demand helps reduce design iterations. An ensemble learning model based on XGBoost is proposed to predict global routing demand using placement-stage features. The XGBoost-based model achieves higher accuracy than CNN- and FCN-based models, improving R² by 0.12 and 0.125, respectively. The inference speed is also significantly faster, up to 14.95×. Feature importance analysis enables reduction of training and inference overhead with minimal accuracy loss.

This paper proposes a Hybrid-Region-Aware Multi-Electrostatic System to address various types of region constraints in the placement problem, which is crucial for meeting the demands of modern chip designs with multiple power domains and providing designers with the flexibility needed to achieve performance goals. Previous methods have attempted to build multiple electrostatic systems for different fence region types to manage this issue. However, these approaches fail to handle situations where instances from different fence region types are allowed to be placed within the same region for a specific type of fence region constraint. To overcome these limitations, we propose generating General electrostatic system that eliminates overlaps between instances across isolated electrostatic systems while minimizing disruptions to the placement result. Additionally, instances assigned to a fence region may initially be displaced from their designated placeable regions due to wirelength forces, requiring extra time and effort to reposition them. To address this issue, we develop a resistive force formulation based on a non-Newtonian fluid model and integrate it into the analytical framework to enhance both convergence stability and efficiency. Experimental results demonstrate the efficiency and effectiveness of our approach, achieving an 11-14% reduction in iteration count compared to MORPH and DREAMPlace 3.0 on academic benchmarks, and a 7.8x reduction in runtime compared to Innovus on industrial benchmarks.

Fence region constraints are essential in cell placement, as they can enhance design convergence speed and improve placement quality. This paper introduces a multilevel framework approach to tackle this challenge while maintaining placement quality and reducing complexity. First, the coarsening stage utilizes a fence region aware clustering to avoid inappropriate groupings. Next, recursive quadratic programming is employed to achieve a better initial cell distribution. Previous methods may result in longer wire-length because they typically assign fence objects to their placement regions before distributing cells over a placement region. To mitigate wirelength increases caused by overly restrictive constraints, our refinement stage uses a three-phase approach to gradually adjust the placement regions of fence objects. Additionally, cells are distributed across desired regions using an analytical placement formulation that includes a fence region aware penalty term. Experimental results demonstrate that our methodology achieves improved wirelength and routability while effectively managing fence region constraints.

Design Rule Checking (DRC) is one of the most important metrices in physical design procedure to evaluate quality of a detail route. The prediction of DRC violation (DRV) in the early stage can reduce the iterations of design procedure and improve the efficiency of the physical design closure. Several researchers have applied machine-learning techniques to predict the DRVs of a detail route at different design stages with various input features. In this paper, we proposed a machine learning model to predict DRVs with the information obtained after placement stage. Specifically, we build a ResNet-like CNN model to predict whether a DRV may occur in a targeted grid after detail route. Our features consist of not only quantified placement information but also layout-image features to take pin accessibility into account for better prediction result. Moreover, we apply an under-sampling technique to select critical training samples to improve the training efficiency. A series of experiments have been conducted and the results show that compared with previous works, our prediction result can outperform Fully Convolutional Network (FCN) based approaches.

Traditional layout migration focuses on area minimization, thus suffered wire distortion, which caused loss of layout topology. A migrated layout inheriting original topology owns original design intention and predictable property, such as wire length which determines the path delay importantly. This work presents a new rectangular topological layout to preserve layout topology and combine its flexibility of handling wires with traditional scan-line based compaction algorithm for area minimization. The proposed migration flow contains devices and wires extraction, topological layout construction, unidirectional compression combining scan-line algorithm with collinear equation solver, and wire restoration. Experimental results show that cell topology is well preserved, and a several times runtime speedup is achieved as compared with recent migration research based on ILP (integer linear programming) formulation.