A time-domain stochastic flash ADC was fabricated using a 12-nm FinFET technology. Its analog input in the voltage domain is transformed into time-domain pulses, which are then sent to a time-to-digital converter (TDC) comprising 405 time comparators. To distinguish the signal timing amplitude, the random input-referred offsets of these comparators are utilized. An input distribution network is employed to broaden the input range of the TDC. A code-mapping calibration method is used to improve the conversion linearity and mitigate the effects of variations in process, voltage, and temperature. Operating at a 12-GS/s sampling rate, the ADC chip consumes 110.7 mW from a 0.8 V supply. It occupies an active area of$480\times 125~\mu \text {m}^{2}$. The ADC achieves an SNDR better than 40.5 dB and an SFDR better than 50.7 dB for input frequencies up to 5.8 GHz.

Aggressively monitoring and tracking system-on-chip (SoC) performance under process/voltage/temperature (PVT) variations is essential for high-performance computing systems. This work observes that different chips of the same SoC design may have different PVT-to-delay sensitivities, which must be carefully considered for accurate chip performance tracking. A learning-based method is then proposed to fit critical path delay for different chips with different PVT-to-delay sensitivities. Experimental results based on the fabricated chip samples of a 7nm SoC have justified the effectiveness of the proposed PVT-sensitive delay fitting method. Compared with the state-of-the-art, our method can achieve excellent performance tracking accuracy when the chip performance is dominated by different critical paths under different PVT conditions.

For an ADC that periodically converts a time-varying analog input, the jitter in the ADC's sampling clock introduces sampling errors, degrading the ADC's dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are then canceled by using a digital differentiator with the acquired jitter estimates. Experiment on a test chip shows that this technique improves the SNR performance of a 12-bit 247-MS/s ADC from 51.9 dB to 56.3 dB when the input is an$\boldsymbol{80}-\mathbf{MHz} -1-\mathbf{dBPS}$sinewave. A sampling clock with 4.89 ps rms jitter drives the ADC.

Monitoring system-on-chip performance under process, voltage, and temperature (PVT) variations is very challenging, especially when the parasitic effects dominate the whole chip performance in advanced process nodes. Most of the previous works presented the performance monitoring methodologies based on known/predicted candidates of critical paths under different operating conditions. However, those methodologies may fail when the critical path is misrecognized or mispredicted. This paper proposes a novel machine-learning based chip performance monitoring methodology to accurately match the chip performance without requiring the information of critical paths under various PVT conditions. The experimental results based on measured chip performance show that the proposed methodology can achieve 98.5% accuracy in the worst case under wide-range PVT variations.