I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

This paper discusses the basic principles of applying data mining in Electronic Design Automation. It begins by introducing several important concepts in statistical learning and summarizes different types of learning algorithms. Then, the experience of developing a practical data mining application is described, including promises that are demonstrated through positive results based on industrial settings and constraints explained in their respective application contexts.

Univariate outlier analysis has become a popular approach for improving quality. When a customer return occurs, multivariate outlier analysis extends the univariate analysis to develop a test model for preventing similar returns from happening. In this context, this work investigates the following question: How simple multivariate outlier modeling can be? The interest for answering this question are twofold: (1) to facilitate implementation of a test model in test application and (2) to ensure robustness of the methodology. In this work, we explain that based on a Gaussian assumption, a simpler covariance-based outlier analysis approach can be sufficient over a more complex density-based approach such as one-class SVM. We show that correlation among tests can be a good metric to rank potential outlier models. Based on these observations a simple outlier analysis methodology is developed and applied to effectively analyze customer returns from two automotive product lines.

This work presents a novel yield optimization methodology based on establishing a strong correlation between a group of fails and an adjustable process parameter. The core of the methodology comprises three advanced statistical correlation methods. The first method performs multivariate correlation analysis to uncover linear correlation relationships between groups of fails and measurements of a process parameter. The second method partitions a dataset into multiple subsets and tries to maximize the average of the correlations each calculated based on one subset. The third method performs statistical independence test to evaluate the risk of adjusting a process parameter. The methodology was applied to an automotive product line to improve yield. Five process parameter changes were discovered which led to significant improvement of the yield and consequently significant reduction of the yield fluctuation.

This work proposes a methodology of knowledge extraction from constrained-random simulation data. Feature-based analysis is employed to extract rules describing the unique properties of novel assembly programs hitting special conditions. The knowledge learned can be reused to guide constrained-random test generation towards uncovered corners. The experiments are conducted based on the verification environment of a commercial processor design, in parallel with the on-going verification efforts. The experimental results show that by leveraging the knowledge extracted from constrained-random simulation, we can improve the test templates to activate the assertions that otherwise are difficult to activate by extensive simulation.

This work presents three pattern mining methodologies for inter-wafer abnormality analysis. Given a large population of wafers, the first methodology identifies wafers with abnormal patterns based on a test or a group of tests. Given a wafer of interest, the second methodology searches for a test perspective that reveals the abnormality of the wafer. Given a particular pattern of interest, the third methodology implements a monitor to detect wafers containing similar patterns. This paper discusses key elements for implementing each of the methodologies and demonstrates their usefulness based on experiments applied to a high-quality SoC product line.

The semiconductor industry has largely gotten off the Moore's law treadmill. Many companies have stopped scaling, realizing that the 65, 45 or 32nm are sufficient for their needs, and relying on foundries to shoulder the risk and capital requirements for advanced nodes. This has resulted in a reduced need for VLSI-oriented research as the industry consolidates and traditional funding sources ramp down. So what does a VLSI researcher do then? Well she or he finds interesting problems to solve in so-called "adjacent" areas. But how does one get started, and how does one find such interesting research areas? This keynote is about two such examples… from VLSI to Proton Radiation Therapy and to Energy Distribution Optimization. It turns out that there are abundant opportunities for those willing to take risks and learn new things. Humanity has invested over $1T in semiconductor R&D, it is time to take that investment and apply its results more broadly!

Novel test detection is an approach to improve simulation efficiency by selecting novel tests before their application [1]. Techniques have been proposed to apply the approach in the context of processor verification [2]. This work reports our experience in applying the approach to verifying a commercial processor. Our objectives are threefold: to implement the approach in a practical setting, to assess its effectiveness and to understand its challenges in practical application. The experiments are conducted based on a simulation environment for verifying a commercial dual-thread low-power processor core. By focusing on the complex fixed-point unit, the results show up to 96% saving in simulation time. The main limitation of the implementation is discussed based on the load-store unit with initial promising results to show how to overcome the limitation.

This work studies the potential of capturing customer returns with models constructed based on multivariate analysis of parametric wafer sort test measurements. In such an analysis, subsets of tests are selected to build models for making pass/fail decisions. Two approaches are considered. A preemptive approach selects correlated tests to construct multivariate test models to screen out outliers. This approach does not rely on known customer returns. In contrast, a reactive approach selects tests relevant to a given customer return and builds an outlier model specific to the return. This model is applied to capture future parts similar to the return. The study is based on test data collected over roughly 16 months of production for a high-quality SoC sold to the automotive market. The data consists of 62 customer returns belonging to 52 lots. The study shows that each approach can capture returns not captured by the other. With both approaches, the study shows that multivariate test analysis can have a significant impact on reducing customer return rates especially during the later period of the production.

Burn-in is a common test approach to screen out unreliable parts. The cost of burn-in can be significant due to long burn-in periods and expensive equipment. This work studies the potential of using parametric test data to reduce the time of burn-in. The experiment focuses on developing parametric test models based on test data collected after 10 hours of burn-in to predict parts likely-to-fail after 24 and 48 hours of burn-in. Our study shows that 24-hour and 48-hour burn-in failures behave abnormally in multivariate parametric test spaces after 10 hours of burn-in. Hence, it is possible to develop multivariate test models to identify these likely-to-fail parts early in a burn-in cycle. This study is carried out on 8 lots of test data from a burn-in experiment based on a 3-axis accelerometer design. The study shows that after 10 hours of burn-in, it is possible to identify a large portion of all parts that do not require longer burn-in time, potentially providing significant cost saving.

introduction Share on Introduction to special section on verification challenges in the concurrent world Authors: Sandip Ray University of Texas at Austin, TX University of Texas at Austin, TXView Profile , Jayanta Bhadra Freescale Semiconductor Inc., Austin, TX Freescale Semiconductor Inc., Austin, TXView Profile , Magdy S. Abadir Freescale Semiconductor Inc., Austin, TX Freescale Semiconductor Inc., Austin, TXView Profile , Li-C. Wang University of California at Santa Barbara, CA University of California at Santa Barbara, CAView Profile , Aarti Gupta NEC Laboratories America, Inc., Princeton, NJ NEC Laboratories America, Inc., Princeton, NJView Profile Authors Info & Claims ACM Transactions on Design Automation of Electronic SystemsVolume 17Issue 3June 2012 Article No.: 19pp 1–3https://doi.org/10.1145/2209291.2209292Published:05 July 2012Publication History 0citation172DownloadsMetricsTotal Citations0Total Downloads172Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This work proposes a wafer probe parametric test set optimization method for predicting dies which are likely to fail in the field based on known in-field or final test fails. Large volumes of wafer probe data across 5 lots and hundreds of parametric measurements are optimized to find test sets that help predict actually observed test escapes and final test failures. Simple rules are generated to explain how test limits can be tightened in wafer probe to prevent test escapes and final test fails with minimal overkill. The proposed method is evaluated on wafer probe data from a current automotive IC with near zero DPPM requirements resulting in improved test quality and reduced test cost.

This paper studies the potential of using wafer probe tests to predict the outcome of future tests. The study is carried out using test data based on an SoC design for the automotive market. Given a set of known failing parts, there are two possible approaches to learn. First a single binary classification model can be learned to model all failing parts. We show that this approach can be effective if the failing parts are compatible in learning. Second, an individual outlier model can be learned for each failing part. We show that this approach is suitable for learning failing parts such as customer returns, where each may have a unique failing behavior. We also show that with Principal Component Analysis (PCA), a learning model can be visualized in two or three dimensional PC space, which facilitates an engineer to manually select or adjust the model.

Customer returns are defective parts that pass all functional and parametric tests, but fail in the field. To prevent customer returns, this paper analyzes wafer probe test data and tries to understand what it takes to screen them out during testing. Because these parts pass all tests, analyzing their signatures based on the original test perspective does not make sense. In this work, we search for a novel test perspective where the test signatures from parametric measurements can be used to separate the returned parts from the rest of population. Our study shows that in order to effectively screen customer returns during wafer test, a multivariate screening methodology is desired. This study is based on analyzing over 1000 parametric wafer probe tests and dies from seven lots, each lot containing one returned part. We demonstrate that analyzing customer returns from a multivariate test perspective leads to robust and conservative results.

Due to the magnitude and complexity of design and manufacturing processes, it is unrealistic to expect that models and simulations can predict all aspects of silicon behavior accurately. When unexpected behavior is observed in the post-silicon stage, one desires to identify the causes and consequently identify the fixes. This paper studies one formulation of the design-silicon mismatch problem. To analyze unexpected behavior, silicon behavior is partitioned into two classes, one class containing instances of unexpected behavior and the other with rest of the population. Classification rule learning is applied to extract rules to explain why certain class of behavior occurs. We present a rule learning algorithm that analyzes test measurement data in terms of design features to generate rules, and conduct controlled experiments to demonstrate the effectiveness of the proposed approach. Results show that the proposed learning approach can effectively uncover rules responsible for the designsilicon mismatch even when significant noises are associated with both the measurement data and the class partitioning results for capturing the unexpected behavior.

Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vddand temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vddselection using TRAM can reduce the total power dissipation by up to 2.5times while attaining an identical predefined limit on errors.

This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while information content measurements guide test clock selection. Exhaustive simulation found trade-offs between reducing the number of clocks, patterns, and chip samples. Substantial cost reduction was obtained with proper clock selection, while minimizing both test patterns and circuit samples required for effective outlier analysis.

Explaining the mismatch between predicted timing behavior from modeling and simulation, and the observed timing behavior measured on silicon chips can be very challenging. Given a list of potential sources, the mismatch can be the aggregate result caused by some of them both individually and collectively, resulting in a very large search space. Furthermore, observed data are always corrupted by some unknown statistical random noises. In this paper, we examine how trying to explain the mismatch observed on silicon can be classified as an ill-posed problem, where ill posed means that the solution may not be unique or stable. Thus, a small change in the observed response can have a large change in the predicted solution. To solve ill-posed problems, a statistical learning theory uses a principle called regularization. This paper proposes using a statistical learning method called support vector (SV) analysis to statistically analyze all known sources of uncertainty with the objective to rank which sources contribute the most to the observed mismatch. Experimental results are presented under different error assumption models to compare two kinds of SV ranking approaches to four other ranking approaches, where some use the idea of regularization and others do not. This paper is concluded by showing a self cross-validation approach to validate the ranking results when there is no true ranking available, as the case with actual silicon.

Explaining the mismatch between predicted timing behavior from modeling and simulation, and the observed timing behavior measured on silicon chips can be very challenging. Given a list of potential sources, the mismatch can be the aggregate result caused by some of them both individually and collectively, resulting in a very large search space. Furthermore, observed data are always corrupted by some unknown statistical random noises. To overcome both challenges, this paper proposes a statistical diagnosis framework that formulates the diagnosis problem as a regression learning problem. In this diagnosis framework, the objective is to rank a set of features corresponding to the list of potential sources of concern. The rank is based on measured silicon path delay data such that a feature inducing a larger unexpected timing deviation is ranked higher. Experimental results are presented to explain the learning method. Diagnosis effectiveness will be demonstrated through benchmark experiments and on an industrial design.

Concurrent interaction of multi-processor systems result in errors which are difficult to find. Traditional simulation-based verification techniques remove the concurrency information by arbitrary schedulings. We present a novel simulation-based technique for SystemC that preserves and exploits concurrency information. Our approach is unique in that we can detect potential errors in an observed execution, even if the error does not actually occur in that execution. We identify synchronization constructs in SystemC and develop predictive techniques for temporal assertion verification and deadlock detection. Our automated potential deadlock detection algorithm works on SystemC programs with semaphores, locks, wait and notify synchronizations and has less overhead compared with assertion verification. We patched SystemC kernel to implement our solution and obtained favorable results on industrial designs.

For sub-65 nm design, there can be many timing effects not explicitly and/or accurately modeled and simulated. For design-silicon timing convergence, this paper describes a novel path-based diagnosis approach that analyzes and ranks potential design related issues causing the unexpected timing effects. We explain in detail how a path can be encoded with a set of diverse "features" based on one's knowledge of the potential issues. We explain how these features can be interpreted differently in a data learning algorithm based on adjusting a so-called kernel function. Then, we explain how kernel-based data learning can be used to rank the importance of features such that a feature contributing the most to design-silicon timing mismatch is ranked the highest. We conclude the paper by showing an application result on an industrial ASIC design.

Multiprocessor systems-on-chip (MPSoC) pose a considerable validation challenge due to their size and complexity. We approach the problem of MPSoC validation through a tool that employs a reusable abstract executable specification written in C++. The tool effectively leverages a simulation-based, trace-driven mechanism. Traces are computed by simulating a system level register-transfer level (RTL) implementation of an MPSoC. The tool then analyzes the traces for correctness by checking them across executions of the abstract executable specification. We have effectively used the tool on various live MPSoC design projects based on the Power Architecture technology (The Power Architecture and Power.org wordmarks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org.). We demonstrate the effectiveness of the technique through results from these projects where we uncovered a number of design errors not found by any other technique.

Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). Hence, in this paper we propose a novel system level leakage aware floorplanner (LEAF) which optimizes floorplans for temperature-aware leakage power along with the traditional metrics of area and wire length. Our floorplanner takes a SoC netlist and the dynamic power profile of functional blocks to determine a placement while optimizing for temperature dependent leakage power, area, and wire length. To demonstrate the effectiveness of LEAF, we implemented our methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and evaluated the trade-off between leakage power and area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage aware floorplanning.

In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitors and (2) delay testing. In the past, delay test data has been overlooked in the correlation study. In this paper, we take path delay testing as an example to illustrate how test data can be incorporated in the overall design-silicon correlation effort. We describe a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We discuss how statistical data mining can be employed for extracting information and show experimental results to demonstrate the potential of the proposed methodology.

As technology scales, it is becoming increasingly difficult for simulation and timing models to accurately predict silicon timing behavior. When a collection of chips fail in timing in a similar way, diagnosis and silicon debug look to find the root-causes for the failure. However, little work has been done to develop a methodology that looks for useful design information in the good-chip data. This paper describes a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We explain how to utilize this methodology for evaluating the risk of timing modeling.

In this work, we present using random forests statistical learning to analyze post-silicon delay test data. We introduce the concept of parametric delay test as a new perspective for extracting more information from delay test. First, a methodology for outlier identification is presented to aid defect characterization of initial sample chips. Second, a methodology for production test is presented, including automated pattern-set reduction analysis. Finally, a strategy for adaptive test is presented.

Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits.

In this paper, we demonstrate the need for considering the floorplan when the leakage power is calculated for a SoC. We proposed a leakage power estimation methodology which considers the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating leakage power. This methodology has been experimented with on three industrial SoC designs and we observed up to a 44.1% difference in leakage power between various floorplans. We believe that our estimation methodology is generic and can be useful for a wide variety of SoCs

As the timing behavior of the good and defective chips become statistical, the traditional notion that there exists a one-dimensional timing boundary to separate the good and defective behavior may no longer be true. This paper studies issues in test optimization for screening statistical delay defects. After the first silicon tapeout, test data learning based on silicon samples can be utilized to optimize the test set for mass production. This approach depends on the availability of known good and known defective samples. This paper focuses the discussion on silicon sample based test optimization. We relate this problem to binary classification and pattern selection to the feature selection problem in statistical learning. Experimental results are presented to explain the methodologies and the new concepts

Moving to new semiconductor technology nodes can dramatically impact the business performance of the SoC company, and its age-old design and manufacturing flows and methodologies. It can also significantly affect its choices of suppliers. This session will provide an overview of changing needs and corresponding management decision criteria to make the right choices from a pool of alternate options.

As timing requirements in today's advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such algorithms capable of diagnosing multiple delay faults. One method uses multiple transition fault models and the other reasons with ternary logic values, thus achieving model independent diagnosis. Experiments are conducted on IS-CAS'85 combinational and full-scan version of ISCAS'89 se-quential circuits corrupted with multiple transition faults. The performance of both algorithms are evaluated and compared. The results show good efficiency and diagnostic resolution.

As VLSI designs grow in complexity and size, errors become more frequent and difficult to track. Recent developments have automated most of the verification tasks but debugging still remains a resource-intensive, manually conducted procedure. This paper bridges this gap as it develops robust automated debugging methodologies that complement verification processes. Unlike prior debugging techniques, the proposed one exploits the hierarchical nature of modern designs to improve the performance and quality of debugging. It also formulates the problem in terms of Quantified Boolean Formula Satisfiability to obtain dramatic reduction in memory requirements, which allows for debugging of large designs. Extensive experiments conducted on industrial and benchmark designs confirm the efficiency and practicality of the proposed approach.

The purpose of statistical timing simulation is to assess the impact of process variations on pattern delays. In this paper, we propose a novel hazard-aware statistical timing simulator. Our simulator characterizes timing hazards in terms of uncertainty windows whose widths are computed as random variables. Given a 2-pattern vector, the simulator estimates the transition times and uncertainty windows at each circuit output as two separate random variables. We demonstrate that this simulator achieves much higher accuracy and robustness than its predecessor. With this improved statistical timing simulator, we study its applications from three perspectives: (1) improving test effectiveness through pattern selection (2) enhancing defect detection by using multiple test frequencies (3) extending defect coverage for different voltages and temperatures. Experimental results are presented to demonstrate the benefits as well as the limitations of using the statistical timing simulator in the context of screening frequency-dependent defects.

The delay variations of a pattern set can come from two sources: (1) Different patterns sensitize different parts of the circuit and result in different delays. (2) The same pattern, applied on different chips, results in different delays because of process variations. For structural delay testing, these pattern variations may result in difficulty for finding an optimal test clock setting, which may significantly impact the defect screening effectiveness. This paper investigates the possibility of applying statistical timing analysis techniques to reduce pattern variations for structural delay testing. We develop an efficient statistical pattern-based timing simulator and devise pattern selection algorithms for reducing such variations. By constructing pattern sets with smaller variations, we show that higher screening effectiveness can be achieved. We present experimental results to demonstrate the advantages of our techniques based on benchmark circuits.

This paper describes the implementation of a novel path-based learning methodology that can be applied for two purposes: (1) In a pre-silicon simulation environment, path-based learning can be used to produce a fast and approximate simulator for statistical timing simulation. (2) In post-silicon phase, path-based learning can be used as a vehicle to derive critical paths based on the pass/fail behavior observed from the test chips. Our path-based learning methodology consists of four major components: a delay test pattern set, a logic simulator, a set of selected paths as the basis for learning, and a machine learner. We explain the key concepts in this methodology and present experimental results to demonstrate its feasibility and applications.

Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean satisfiability. This formulation takes advantage of modern Boolean satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean satisfiability provides an effective platform for sequential logic debugging.

The use of functional vectors has been an industry standard for speed binning purposes of high performance ICs. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural testing an effective alternative to functional testing for speed binning, structural patterns need to correlate with functional test frequencies closely. We investigate the correlation between functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/spl trade/ instruction set architecture.

While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementation styles. We present a methodology and a tool, the implementation-dependent array power (IDAP) estimator, that model power dissipation in SRAM-based arrays accurately based on a high-level description of the array. The models are parameterized by the array operations and various technology dependent parameters. The methodology is generic and the IDAP tool has been validated on industrial designs across a wide variety of array implementations in the e500 processor core (e500 is the Motorola processor core that is compliant with the PowerPC Book E architecture). For these industrial designs, IDAP generates high-level estimates for dynamic power dissipation that are accurate with an error margin of less than 22.2% of detailed (layout extracted) SPICE simulations. We apply the tool in three different scenarios: 1) identifying the subblocks that contribute to power significantly; 2) evaluating the effect of bitline-voltage swing on array power; and 3) evaluating the effect of memory bit-cell dimensions on array power.

was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a ”dual-rail ” symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and datapath domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the Memory Management Unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process. I.

Custom VLSI design at the switch level is commonly applied when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models are created manually from the switch level models---a tedious, error-prone process requiring experienced DFT engineers. This paper presents an automated flow for creating gate level test models from circuits at the switch level. The proposed flow utilizes Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and represent them at a higher level of abstraction. We present experimental results, which demonstrate that the automated flow is capable of producing gate models that meet the ATPG requirements and are comparable to manually created ones.

We present a formal logic verification methodology for combinational circuits. The method uses simulation, logic diagnosis and ATPG to identify circuit lines that implement equivalent logic functions efficiently. One advantage of the proposed technique is that it identifies line equivalences under controllability and observability don't care conditions, while not suffering from false negatives. The method is easy to implement, and, due to its general nature, existing techniques can benefit from ideas described here. We also give implementation details and present experiments to confirm its potential.

Custom VLSI design at the switch level is commonly needed when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models for custom logic are created manually from the switch level models - a tedious, error-prone process requiring experienced DFT engineers. This paper presents an automated flow for creating gate level test models from circuits at the switch level. Besides providing comparable test quality, the test model created by automated flow maintains structural similarity to the original switch-level circuit which facilitates failure analysis greatly. The automated flow has been in use for the past several years within Motorola for the high performance processor family implementing the PowerPC instruction set architecture. We present experimental results on MPC7455.

In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic models: the Williams-Brown (WB) model and the Mercer-Park-Grimaila-Dworak (MPGD) model. In the WB-model, the defect coverage is replaced by the n-detection transition fault coverage. We first demonstrate that both logic models may fail to predict the detection of statistical timing defects. Then, we propose an improved WB model based upon selection of the hard-to-detect transition faults. We show that, by selecting a proper subset of the hard-to-detect transition faults, the detection behavior of these faults can correlate well to the detection behavior of statistical timing defects. We explain our findings through statistical delay defect injection and simulation, and report results based upon various benchmark circuits.

In this paper, we presented a new transition ATPG methodology flow for scan-based design using broad-side test format. A replicate and reduce (RR) circuit transform is introduced, which maps the two time frame processing of transition fault ATPG to a single time frame processing on duplicated iterative blocks with reduced connection. A complete ATPG methodology flow is proposed to generate high coverage transition test patterns both fast and efficiently. Experimentation results on several circuits from next generation Motorola microprocessor design are presented to show the effectiveness of our approach.

A well-known problem in timing verification of VLSI circuits using static timing analysis tools is the generation of false timing paths. This leads to a pessimistic estimation of the processor speed and wasted engineering effort spent optimizing unsensitizable paths. Earlier results have shown how ATPG techniques can be used to identify false paths efficiently [6],[9], as well as how to bridge the gap between the physical design on which the static timing analysis is based and the test view on which ATPG technique is applied to identify false paths [9]. In this paper, we will demonstrate efficient techniques to identify more false timing paths by utilizing information from an ordered list of timing paths according to the delay information. More than 10% of additional false timing paths out of the total timing paths analyzed are identified compared to earlier results on the MPC7455, a Motorola processor executing to the PowerPC™.

Most industrial memories have an external word-width of more than one bit. However, most published memory test algorithms assume 1-bit memories; they will not detect coupling faults between the cells of a word. This paper improves upon the state of the art in testing word-oriented memories by presenting a new method for detecting state coupling faults between cells of the same word, based on the use of m-out-of-n codes. The result is a reduction in test time, which varies between 26 and 38%.

An incremental simulation-based approach to fault diagnosis and logic debugging is presented. During each iteration of the algorithm, a single suspicious location is identified and fault modeled such that the functionality of the new design becomes "closer" to its specification. The method is based on a simple and, at a first glance, counter-intuitive theoretical result along with a number of heuristics which help avoid the exponential complexity inherent to the problems. Experiments on multiple design errors and multiple stuck-at faults confirm its effectiveness and accuracy, which scales well with increasing number of errors.

In the past, symbolic trajectory evaluation (STE) has been shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD (ordered boolean decision diagrams) sizes would often blow up. In this paper, we propose the use of both an ATPG-based justification engine and symbolic simulation to facilitate the application of STE proof methodology for array systems. Our method translates a given verification problem instance into ATPG justification objectives, and partitions a given design into ATPG and symbolic simulation domains. Then, by developing a scheme that enables the ATPG justification engine to work closely with the symbolic simulator, the runtime OBDD sizes during each symbolic simulation run can be limited. We demonstrate the effectiveness of our approach by verifying the memory management units (MMU) in Motorola high-performance microprocessors. The verification of a MMU as a whole was not possible before because of the OBDD size blow-up problem when symbolic simulation is used in the STE proof process.

Technology dependent logic optimization is usually carried through a sequence of design rewiring operations. In Veneris et al (Proc. Asian-South-Pacific Design Automation Conf., pp. 479-484, 2001), a new design rewiring method is proposed that combines error diagnosis and correction techniques with ATPG. In this work, we examine its complexity and we arrive to a new set of results with interesting theoretical and practical applications. We also present experiments that confirm the competitiveness of the approach and motivate future work in the field.

When testing high-performance custom designs, the implementation models for these designs can often be missing or only available late in a design cycle. To facilitate test preparation for these designs and to ensure their test quality, this paper studies ATPG approaches whose resulting test quality are less design model dependent. These ATPG approaches do not depend on the internal implementation structure of a design and utilizes multiple detection techniques to achieve the desired test quality. As a result, test quality results are transferable from one model representation to another. For high-performance custom designs, we discover that without explicit testing of the internal faults, an ATPG is able to deliver better quality performance than traditional model-dependent approaches. Experience and experimental results from a recent Motorola high-performance microprocessor is reported and discussed.

Equivalence checking between Register Transfer Level (RTL) descriptions and transistor level descriptions of custom memories is an important step in the design flow of high performance microprocessors. Equivalence checking can be done with or without the knowledge of state mapping between the two descriptions. We present evidence that because of state mapping, our verification technique exercises system behavior that exposes hard-to-detect bugs that might otherwise go undetected. This paper defines Crossover Bugs (CB's) that can be present in scan-based custom designs and that are inherently hard-to-detect without state mapping. We demonstrate that such bugs can be missed by equivalence checking techniques that do not have state mappings between the two descriptions. By identifying the state correspondences between the RTL and the transistor implementation of custom memories, a more rigorous equivalence check can be performed compared to traditional equivalence checking methods such as product machine constructions. We also compare the time and memory complexities of crossover bug detection capability of the two equivalence checking approaches. We conclude with experimental results of CB detection on some of the custom designed embedded memories of Motorola's MPC 7455 microprocessor (compliant with IBM's PowerPC instruction set architecture).

Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints such as area, power, or delay. Recently, automated test pattern generation (ATPG)-based design rewiring techniques for technology-dependent logic optimization have gained increasing popularity. In this paper, the authors propose a new operational framework to design rewiring that uses ATPG and diagnosis algorithms. They also examine its complexity requirements and discuss different implementation tradeoffs. To perform this study, the authors reduce the problem of design rewiring to the process of injecting a redundant set of multiple pattern faults. This formulation arrives at a new set of results with theoretical and practical applications. Experiments demonstrate the competitiveness of the approach and motivate future work in the area.

Logic optimization is the step of the VLSI design cycle where the designer performs modifications on a design to satisfy di#erent constraints such as area, power or delay. Recently, ATPG-based design rewiring techniques for logic optimization have gained increasing popularity. In this paper we propose a novel ATPG-based design rewiring methodology that borrows from previous design error diagnosis and correction techniques. We also present examples and experiments that indicate the added potential of our approach which is expected to provide a "powerful" route to design optimization. 1 Introduction Logic optimization is the step of the VLSI design cycle where the designer modifies the netlist obtained by synthesis tools to achieve di#erent constraints such as minimize the area, reduce power consumption, satisfy timing constraints, reduce switching noise or improve the testability of the final circuit. Recently, ATPG-based optimization techniques [6] [7] [8] [9] [10] [12] have gained i...

Static timing anaylsis sets the industry standard in the design methodology of high speed/performance microprocessors to determine whether timing requirements have been met. Unfortunately, not all the paths identified using such analysis can be sensitized. This leads to a pessimistic estimation of the processor speed. Also, no amount of engineering effort spent on optimizing such paths can improve the timing performance of the chip. In the past we demonstrated initial results of how ATPG techniques can be used to identify false paths efficiently. Due to the gap between the physical design on which the static timing analysis of the chip is bused and the test view on which the ATPG techniques are applied to identify false paths, in many cases only sections of some of the paths in the full-chip were analyzed in our initial results. In this paper, we will fully analyze all the timing paths using the ATPG techniques, thus overcoming the gap between the testing and timing analysis techniques. This enables us to do false path identification at the full-chip level of the circuit. Results of applying our technique to the second generation G4 PowerPC/sup TM/ will be presented.

Custom circuits, in contrast to those synthesized by automatic tools, are manually designed blocks of which performance is critical to the full chip operation. Testing these blocks represents a major DFT challenge and hence, a crucial time-to-market factor in microprocessor design flow. This paper compares three industry-adopted methodologies for testing custom blocks. Pros and cons are analyzed and discussed based on factors such as stability of the methodologies, resulting sizes of gate-level models, ATPG process, and testing quality in terms of non-target defect detection. Experience and results from a recent PowerPC microprocessor are reported.

This paper describes the use of Symbolic Trajectory Evaluation (STE), a modified form of symbolic simulation, to verify the equivalence between RTL and transistor-level representations of on-chip custom memories for the latest PowerPC microprocessor. The validation of embedded memories and their associated control logic poses a special problem for traditional formal equivalence checking tools due to the inherently sequential and self-timed nature of the internal control logic and the large number of state-holding elements. The use of the VERSYS STE engine to validate these custom memories is illustrated. We present our array verification methodology, discuss some of the results of our approach, and outline plans for future development.

Testing of modern microprocessor designs remains a challenging problem. At Motorola's Somerset Design Center, we rely heavily on Design-For-Test (DFT) to address these challenges. To date our efforts have been very successful. This paper reviews our DFT methodology and how the DFT group is dealing with the new challenges that are facing PowerPC/sup TM/ microprocessor designs.

Custom circuits, in contrast to those synthesized by automatic tools, are manually designed blocks of which performance is critical to the full chip operation. Testing these block represents a major challenge and hence, a crucial time-to-market factor in micro-processor design flow. This paper investigates various methodologies for testing custom blocks. Issues of efficiently obtaining proper circuit model for ATPG tools as well as producing quality tests are analyzed and discussed. Tradeoffs among various methods are analyzed and compared. Experience and results based on recent PowerPC microprocessors will be reported.

For verifying complex sequential blocks such as microprocessor embedded arrays, the formal method of symbolic trajectory evaluation (STE) has achieved great success in the past [[3], [5], [6]]. Past STE methodology for arrays requires manual creation of "assertions" to which both the RTL view and the actual design should be equivalent. In this paper, we describe a novel method to automate the assertion creation process which improves the efficiency and the quality of array verification. Encouraging results on recent PowerPC arrays will be presented.

Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for array design validation have been proposed and had great success, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, we propose a new way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. This technique provides a systematic way for the evaluation of the quality of various validation approaches. Experimental results using different validation approaches on recent PowerPC microprocessor arrays are reported.

Recently, formal verification has become more a part of the VLSI design methodology. Formally verifying a design guarantees 100% coverage and negates the need to do simulation. Theoretically, 100% coverage is very appealing and formal verification looks to be the panacea to solve the coverage problem. However, there are many practical considerations in deploying formal verification in real design environments. These considerations if not evaluated can lead to ineffective and even erroneous formal verification methodologies. In this paper we show how to make formal verification a successful part of a design methodology by paying attention to practical considerations and knowing the limitations of formal verification. We show the errors that can result by making over generalized assumptions and how they can be avoided. We do this in the context of the design of PowerPC microprocessors. We limit ourselves to a formal verification technique commonly used in our design methodology-boolean equivalence checking.

Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for army design validation have been proposed and had great success, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, the authors propose a way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way for the evaluation of the quality of various validation approaches at both logic and transistor levels. Experimental results using different validation approaches on PowerPC microprocessor arrays will be reported.

Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for array design validation have been proposed and had great success [Ganguly et al. 1996; Pandey et al. 1996, 1997; Wang and Abadir 1997], little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, we measure the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way to evaluate various validation approaches at both logic and transistor levels. Experimental results on recent PowerPC microprocessor arrays will be discussed and reported.

In this paper we report on new techniques for verifying contentaddressable memories (CAMs), and demonstrate that these techniqueswork well for large industrial designs. It was shown in [Formal verification of PowerPC(TM) arrays using symbolic trajectory evaluation], that theformal verification technique of symbolic trajectory evaluation (STE)could be used successfully on memory arrays. We have extended thatwork to verify what are perhaps the most combinatorially difficultclass of memory arrays, CAMs. We use new Boolean encodings toverify CAMs, and show that these techniques scale well, in that spacerequirements increase linearly, or sub-linearly, with the various CAMsize parameters.In this paper, we describe the verification of two CAMs froma recentPowerPC microprocessor design, a Block Address Translation unit(BAT), and a Branch Target Address Cache unit (BTAC). The BATis a complex CAM, with variable length bit masks. The BTAC is a64-entry, 64-bits per entry, fully associative CAM and is part of thespeculative instruction fetch mechanism of the microprocessor. Webelieve that ours is the first work on formally verifying CAMs, and webelieve our techniques make it feasible to efficiently verify the varietyof CAMs found on modern processors.

Test and validation of embedded array blocks remain as a major challenge in today's processor design environment. The difficulty comes from two folds. First, the sizes of the arrays are too large to be handled by the most sophisticated sequential ATPG tools. On the other hand, the complex timing and control make it hard to model these arrays as well-defined transparent blocks which combinational ATPG tools can understand. This paper describes a novel methodology for test and validation of complex array blocks in PowerPC RISC microprocessors. Unlike traditional ATPG methods, our methodology uses formal techniques to functionally verify the arrays and then derive tests from the verification results. The superiority of these tests over the traditional ATPG tests will be discussed and shown at the transistor level through experiments on various recent PowerPC array designs.

A new Boolean function representation scheme, the Indexed Binary Decision Diagram (IBDD), is proposed to provide a compact representation for functions whose Ordered Binary Decision Diagram (OBDD) representation is intractably large. We explain properties of IBDDs and present algorithms for constructing IBDDs from a given circuit. Practical and effective algorithms for satisfiability testing and equivalence checking of IBDDs, as well as their implementation results, are also presented. The results show that many functions, such as multipliers and the hidden-weighted-bit function, whose analysis is intractable using OBDDs, can be efficiently accomplished using IBDDs. We report efficient verification of Booth multipliers, as well as a practical strategy for polynomial time verification of some classes of unsigned array multipliers.

In this paper we discuss the methodology used on PowerPC RISC microprocessors to verify the correctness of embedded array blocks. The functional behavior of these blocks cannot be verified using traditional functional simulators since the search space is too large. Our methodology combines the use of equivalence checking formal methods, simulation using ATPG test vectors, and symbolic trajectory evaluation We discuss how these techniques are applied to verify the operation of an array in during design representation formats. We also discuss how these techniques can be used for checking the consistency of different design representations.

The paper discusses techniques that help a designer to consider testability features early in the design cycle. The behavioral specification of a design is used to perform high level testability analysis, based on which behavioral modifications for testability are suggested to the designer. Results show that the overhead for incorporating these modifications is minimal.>

This paper describes the partitioning subsystem of MCC's Testability Insertion Guidance ExpeRt system (TIGER) [2]. TIGER addresses Design for Testability issues by employing a divide and conquer strategy which permits auser to analyze testability problems early in a design cycle, and make intelligent decisions about the applicability of various test methods to circuit partitions. This paper describes the methodology used in Tiger to partition hierarchical designs for test purposes.

An overview is given of a knowledge-based testability insertion guidance expert system (TIGER) that provides designers with a systematic approach for creating complex, testable designs. Specifically, this system identifies testability problems early in the design cycle, formulates a test strategy for the design, does 'what-if' exploration of DFT (design for testability) solutions, plans the invocation of gate-level test tools on design partitions, and develops a low-cost solution to the test problem that satisfies the design goals and constraints. Also described are the experimental results obtained using the system on several real designs.>

A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test patterns that were developed to detect single stuck-line faults in the gate-level implementation are used instead to compare the gate-level implementation with the functional-level specification. In the presence of certain hypothesized design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. It is shown that the class of design errors that can be detected in this way is very large.>

In this correspondence, the concept of a test schema which describes how a test methodology is to execute is introduced. We also introduce the powerful concept of an I path which is used to transfer data unchanged from one place in a circuit to another. The process of embedding a test schema into an actual circuit is described. This produces a test plan for the circuit which specifies the sequence of actions that need to be carried out to execute the test. A theory of test plan execution overlap is presented, and is used as the basis for constructing test schedules with optimal execution times.

This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.