Demo Data from EDBT 2026 / reviewers in the wild / expert
Nobuaki Yoshida
dblp:85/2200
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 91% Processor architecture and microarchitecture · 9% | |
| Theoretical computer science
1 paper |
Automata and formal languages · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.0 | 1 | 1991 | Pseudorandom Rounding for Truncated Multipliers · IEEE Trans. Computers 1991 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1991 | Pseudorandom Rounding for Truncated Multipliers · IEEE Trans. Computers 1991 |
Integrated circuit design › digital circuit design › arithmetic circuit design
truncated multiplier |
0.0 | 1 | 1991 | Pseudorandom Rounding for Truncated Multipliers · IEEE Trans. Computers 1991 |
Processor architecture and microarchitecture › computer arithmetic
floating-point arithmetic |
0.0 | 1 | 1991 | Pseudorandom Rounding for Truncated Multipliers · IEEE Trans. Computers 1991 |
Automata and formal languages › finite automata › finite state machine testing
checking experiments |
0.0 | 1 | 1975 | Comments on "Checking Experiments for Sequential Machines" · IEEE Trans. Computers 1975 |
Automata and formal languages › finite automata
sequential machines |
0.0 | 1 | 1975 | Comments on "Checking Experiments for Sequential Machines" · IEEE Trans. Computers 1975 |
Methods — techniques the papers use, named apart from their topics
pseudorandom rounding · 0.0numerical simulation · 0.0counterexample construction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1999 | Type Inference with Rank 1 Polymorphism for Type-Directed Compilation of MLabstractThis paper defines an extended polymorphic type system for an ML-style programming language, and develops a sound and complete type inference algorithm. Different frdm the conventional ML type discipline, the proposed type system allows full rank 1 polymorphism, where polymorphic types can appear in other types such as product types, disjoint union types and range types of function types. Because of this feature, the proposed type system significantly reduces the value-only restriction of polymorphism, which is currently adopted in most of ML-style impure languages. It also serves as a basis for efficient implementation of type-directed compilation of polymorphism. The extended type system achieves more efficient type inference algorithm, and it also contributes to develop more efficient type-passing implementation of polymorphism. We show that the conventional ML polymorphism sometimes introduces exponential overhead both at compile-time elaboration and run-time type-passing execution, and that these problems can be eliminated by our type inference system. Compared with a more powerful rank 2 type inference systems based on semi-unification, the proposed type inference algorithm infers a most general type for any typable expression by using the conventional first-order unification, and it is therefore easily adopted in existing implementation of ML family of languages. Atsushi Ohori, Nobuaki Yoshida |
ICFP | 2 |
| 1991 | Pseudorandom Rounding for Truncated MultipliersabstractAn economical, unbiased, overflow-free rounding scheme for multiplication of multiple-precision floating-point numbers is proposed. The scheme, called pseudorandom rounding, saves multiplications of lower bits and makes use of statistical properties of bits around the least significant bit of products in order to compensate for truncated parts. The method is deterministic, and inputs are commutable. The validity of the rounding is verified by numerical simulation.> Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa |
IEEE Trans. Computers | 1 |
| 1975 | Comments on "Checking Experiments for Sequential Machines"abstractThis correspondence comments on the statement, described in the above-mentioned paper,1 which follows after a few definitions characterizing input-output sequences for the design of checking experiments. Namely, a counterexample will be shown for one of the two statements. Furthermore, three generalized properties useful to demonstrate the above counterexample are presented. Y. Wakimura, Nobuaki Yoshida |
IEEE Trans. Computers | 2 |