This paper presents the characterization of the new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; and reducing power consumption and silicon area by means of new memory cells designed with full-custom approach. The design was submitted in December 2016; the prototypes were fabricated and packaged in a 17 × 17 Ball Grid Array (BGA) standalone package. Prototype characterization confirms the chip functionality. The final chip will be assembled in a System In Package (SiP) together with a bare FPGA die.

This paper presents a new Content Addressable Memory (CAM) cell, designed in two variants (inverting and non-inverting), and optimized for power consumption. The cells are designed in 28 nm CMOS technology, using a fully-CMOS approach. If one of the bits in a word is not matching, the corresponding cell sends a "kill" signal to the cascaded cell to inhibit further switching. Thanks to this feature, the designed CAM array requires less than 0.7 fJ/bit per comparison. A prototype containing 217words of 18 bits each has been fabricated and it has proven to be functional.

A digitally-controlled ring oscillator for phase locked loops designed in a commercial 28 nm CMOS technology is presented. Its operating frequency ranges from 2 GHz to 3.2 GHz. A much wider frequency range available in typical case compensates for frequency limitations induced by process variability. The circuit is based on a ring oscillator in which the switching speed of the inverters is controlled by a stream of digital bits. This oscillator is part of a digital PLL, in which the frequency of this oscillator is divided by 8 and used to track an incoming clock signal between 250 MHz and 400 MHz. This circuit is used to obtain eight different clock signals, synchronized with the reference one, to be distributed in massive parallel computation VLSI devices in order to spread the total power consumption of the chip across the reference clock cycle. Post-layout simulations demonstrate that the device is fully compliant in every process corner with the requirements of the future associative memory chip for the track trigger of the ATLAS detector at CERN.

This paper presents the characterization of an input/output interface circuit designed for multi-purpose pattern recognition applications compatible with low-voltage fully differential signaling (LVDS) standard. The driver and receiver circuits described in this work has been designed and fabricated in a 28 nm CMOS technology. The prototype chip has been mounted on a printed circuit board with physical characteristics similar to the real application case and fully validated up to 1 Gb/s with input random patterns.

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose Boolean functions with separate lattices, according to the P-circuits decomposition scheme, and then to implement the decomposed blocks with physically separated regions in a single lattice. Experimental results show that about 35% of the considered benchmarks achieve a smaller area when implemented using the proposed decomposition for switching lattices, with an average gain of at least 24%.

A low-power, wide temperature range, radiation tolerant CMOS voltage reference is presented. The proposed reference circuit exhibits a voltage deviation of 0.8mV for 3-MeV protons total ionization dose of 2Mrad and a voltage deviation of 3.8mV for 10-keV X-rays total ionization dose of 4Mrad while being biased at the nominal supply voltage of 0.75V during X-ray irradiation. In addition, the circuit consumes only 4μW and exhibits a measured Temperature Drift of 15ppm/°C for a temperature range of 190°C (−60°C to 130°C) at the supply voltage of 0.75V. It utilizes only CMOS transistors, operating in the subthreshold regime, and poly-silicon resistors without using any diodes or external components such as compensating capacitors. The circuit is radiation hardened by design (RHBD), it was fabricated using TowerJazz Semiconductor's 0.18μm standard CMOS technology and occupies a silicon area of 0.039mm2. The proposed voltage reference is suitable for high-precision and low-power space applications.

Boolean functional decomposition techniques built on top of Shannon cofactoring have been discussed in various applications of logic synthesis targeting reductions in area, delay and power. In this paper we investigate a generalization of decomposition based on Shannon cofactoring by means of non-orthonormal projection functions. We provide an approximation algorithm, by showing a constant approximation ratio between its result and the best solution. Experimental results in logic restructuring to reduce area and switching power show significant gains with respect to standard Shannon cofactoring, for even shorter computation time.

In this paper, we present a model to derive statistical properties of digital noise due to logic transitions of gates in a fully CMOS combinational circuit. Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a complex IC makes digital switching a cognitively stochastic process. For a combinational logic network, we can model digital switching currents as stationary shot noise processes, deriving both their amplitude distributions and their power spectral densities. From the spectra of digital currents, we can also calculate the spectral components and the rms value of disturbances injected into the on-chip power supply lines. The stochastic model for switching currents has been validated by comparing theoretical results with circuit simulations.

A software tool named TOSCA (Tool for Oversampled Switched-Capacitor A/D Converter Analysis) is described. The simulator is behavioral, general purpose and fully user-friendly. Because a set of basic building blocks is available, generic switched-capacitor noise-shaping A/D converters can be analyzed simply by building netlist file. Two hierarchical levels have been considered for circuit description: block level for subcircuits like quantizers and digital filters, and component level for subcircuits like the integrators where switches, capacitors and operational amplifiers are used as building elements. The developed models allow the most relevant nonideal parameters of the components to be taken into account, and a set of postprocessing facilities allows extensive analysis of the circuits. The program is written in C language, uses dynamic memory allocation, and is very fast.>