Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas E. Tkacik
dblp:85/2403
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
2 papers |
Hardware security and side channels · 62% Systems and software security · 31% Cryptographic primitives and cryptanalysis · 8% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
hardware trojan |
0.3 | 1 | 2017 | Security Assurance for System-on-Chip Designs With Untrusted IPs · IEEE Trans. Inf. Forensics Secur. 2017 |
Systems and software security › runtime security
runtime security monitoring |
0.3 | 1 | 2017 | Security Assurance for System-on-Chip Designs With Untrusted IPs · IEEE Trans. Inf. Forensics Secur. 2017 |
Cryptographic primitives and cryptanalysis
random number generation |
0.0 | 1 | 2002 | A Hardware Random Number Generator · CHES 2002 |
Cryptographic primitives and cryptanalysis › random number generation
true random number generator |
0.0 | 1 | 2002 | A Hardware Random Number Generator · CHES 2002 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 2002 | A Hardware Random Number Generator · CHES 2002 |
Methods — techniques the papers use, named apart from their topics
security policy checking · 0.3design-for-debug · 0.3hardware random number generation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Security Assurance for System-on-Chip Designs With Untrusted IPsabstractModern system-on-chip (SoC) designs involve integration of a large number of intellectual property (IP) blocks, many of which are acquired from untrusted third-party vendors. An IP containing a security vulnerability-whether inadvertent or malicious-may compromise the trustworthiness of the entire SoC, e.g., by leaking sensitive information or causing execution failures at key points. Existing functional validation approaches, post-manufacturing tests, and IP trust verification techniques are inadequate to accomplish comprehensive system-level security assurance in the presence of untrusted IPs. In this paper, we analyze security issues at the SoC level caused by untrusted IPs. We also propose a novel, resilient SoC security architecture to ensure trusted SoC operation with untrusted IPs. Our architecture realizes fine-grained IP-trust aware security policies in an efficient security policy checker that enables run-time monitoring of security issues arising from untrusted IPs. It also exploits on-chip design-for-debug architecture to ensure trusted information flow from IP blocks to the security policy checker. Unlike existing solutions to the untrusted IP problem, which rely on verification of IP trust before they are integrated into an SoC, the proposed approach follows a fundamentally different architecture-level solution based on run-time resilience. We demonstrate the effectiveness of this framework for system protection using several illustrative practical use cases. We also provide experimental results to show that the overhead of the proposed architecture is modest on representative SoC designs. Abhishek Basak, Swarup Bhunia, Thomas E. Tkacik, Sandip Ray |
IEEE Trans. Inf. Forensics Secur. | 3 |
| 2005 | An Advanced Trusted Platform for mobile phone devices
Carlin R. Covey, Mark D. Redman, Thomas E. Tkacik |
Inf. Secur. Tech. Rep. | 3 |
| 2002 | A Hardware Random Number Generator
Thomas E. Tkacik |
CHES | 1 |