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Theodore Sabety

dblp:85/2604 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 78% Parallel and multicore computing · 22%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.011985
Layout design-lessons from the Jedi designer (tutorial session) · DAC 1985
Electronic design automation › physical design
placement and routing		 0.011985
Layout design-lessons from the Jedi designer (tutorial session) · DAC 1985
Electronic design automation
high-level synthesis		 0.011984
The semi-automatic generation of processing element control paths for highly parallel machines · DAC 1984
Parallel and multicore computing › parallel architecture
parallel machine design		 0.011984
The semi-automatic generation of processing element control paths for highly parallel machines · DAC 1984
Electronic design automation › physical design
layout compaction		 0.011985
Layout design-lessons from the Jedi designer (tutorial session) · DAC 1985
YearPublicationVenuePosition
1985 Layout design-lessons from the Jedi designer (tutorial session)
abstract
Today there are many tools available that automatically produce IC layouts; however, designers are reluctant to accept the results produced by these programs. This session will explore the underlying assumptions and basic algorithms used in the design and development of these systems and will introduce the approach of the Jedi Designer system. The information presented in this tutorial will provide a basis for evaluating existing and proposed algorithms for placement, routing, and compaction of IC layouts.
Susan L. Taylor, Roderic Beresford, Theodore Sabety
 DAC3
1985 The multiple-processor PPS chip of the NON-VON 3 supercomputer
David E. Shaw, Theodore Sabety
 Integr.2
1984 The semi-automatic generation of processing element control paths for highly parallel machines
Theodore Sabety, David E. Shaw, Brian Mathies
 DAC1