Micro-displays are ubiquitous in portable electronics, ranging from consumer products to specialized industrial and medical devices including heads-up displays (HUDs), and augmented reality (AR) and virtual reality (VR) headsets. To increase the battery life of portable electronics, it is important to address power consumption in micro-displays, which is the most power-hungry block in these devices. With the improved power efficiency of display media, the power consumption of the display backplane is still high, especially while streaming video. Therefore, to reduce overall power consumption, it is important to reduce the power consumption of the display backplane. This work investigates the impact of column segmentation techniques and row charge sharing on reducing the power consumption of the display backplane. The measurement result of a VGA (480 × 640) micro-display implemented in TSMC 65 nm technology shows a 18.4% reduction in the average total power consumption of the display backplane using a dual-column driver with column segmentation architecture. • Study of various column segmentation architectures to reduce column driver power. • Use of row charge sharing mechanism to reduce power consumption of row driver. • Understanding of effect of image pattern on display backplane power consumption. • Understanding the effect of increase in display resolution or refresh rate on power consumption of backplane.

The micro-display market is expanding rapidly due to the increasing adoption of smartwatches and VR/AR head-mounted devices, creating strong demand for ultra-low-power display solutions to prolong battery life. Among various micro-display architectures, the digitally driven Pulse-Width Modulation (PWM) technique is preferred on CMOS backplanes due to its immunity to analog storage errors and the elimination of power-hungry digital-to-analog converters (DACs). However, conventional PWM-based digital driving schemes require repeated pixel programming within each frame, causing large column-line capacitance switching and substantial power dissipation in the display backplane. This paper presents an AND-Logic embedded 7T SRAM memory-based backplane circuit that minimizes pixel programming to only twice per frame, significantly reducing column line transitions and driver power. Fabricated in 65-nm CMOS, the proposed design achieves an 18.6% reduction in display backplane power compared to the conventional architecture. Furthermore, compared to the prior 8T AND-Logic embedded SRAM, the proposed SRAM cell achieves a 12.7% reduction in pixel memory area and a 4.9% reduction in backplane’s power consumption according to post-layout simulations, demonstrating its suitability for compact, power-efficient micro-display systems.

Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively. • This paper proposed a very low-power flip-flop with only two single-phase clock transistors. • Proposed flip-flop is the most power-efficient amongst all considered. state-of-the-art flip-flops for data activities in the range of 0 – 45%. • Test-chip implemented in TSMC 65nm GP PDK validates the power savings of the proposed flip-flop over 18TSPC, and TGFF.

Microdisplays are a key component in many contemporary portable electronic systems. Microdisplays consume a large fraction of the overall energy of the system, and therefore, there is a desire to reduce its energy and extend the battery life. This paper proposes circuit techniques to recycle energy in the row driver and reduce its dynamic power consumption. The measurement results on proof-of-concept arrays implemented in TSMC 65 nm technology show a 24%, 29%, and 30% reduction in the power consumption of the row driver using the one-capacitor, two-capacitor, and direct energy recycling techniques, respectively. Applying these techniques reduces up to more than 45% of the dynamic power consumption of the row driver.

Strong physical unclonable functions (PUFs) provide a low-cost authentication primitive for resource-constrained devices. However, most strong PUF architectures can be modeled through learning algorithms with a limited number of CRPs. In this article, we introduce the concept of nonmonotonic response quantization for strong PUFs. Responses depend not only on which path is faster but also on the distance between the arriving signals. Our experiments show that the resulting PUF has increased security against learning attacks. To demonstrate, we designed and implemented a nonmonotonically quantized ring oscillator-based PUF in 65-nm technology. Measurement results show nearly ideal uniformity and uniqueness with a bit error rate of 13.4% over the temperature range from 0 °C to 50 °C.

Secret keys can be extracted from the power consumption or electromagnetic emanations of unprotected devices. Traditional countermeasures have a limited scope of protection and impose several restrictions on how sensitive data must be manipulated. We demonstrate a bit-serial RISC-V microprocessor implementation with no plain-text data. All values are protected using Boolean masking. Software can run with little to no countermeasures, reducing code size and performance overheads. Unlike previous literature, our methodology is fully automated and can be applied to designs of arbitrary size or complexity. We also provide details on other key components, such as clock randomizer, memory protection, and random number generator (RNG). The microprocessor was implemented in 65-nm CMOS technology. Its implementation was evaluated using NIST tests and side-channel attacks. Random numbers generated with our RNG pass on all NIST tests. The side-channel analysis on the baseline implementation extracted the advanced encryption system (AES) key using only 375 traces, while our secure microprocessor was able to withstand attacks using 20M traces.

This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to the sources as well as to the body of the critical sensing transistors. We simulated and fabricated the proposed DIBBSA architecture with various operational modes in 65-nm CMOS technology to analyze body biasing's effectiveness in mitigating the offset. The standard deviation of offset ( σOS) was measured over 5120 SAs in 10 ICs. The iso-gate area reduction in σOSfor the proposed DIBBSA-FL and DIBBSA-PD modes resulted in 68.1% and 61.9% compared to conventional Current Latch SA (CLSA) and 24.1% and 18.1% compared to Voltage Latch SA (VLSA) at 0.4 V supply and 25 °C, respectively. Carried out measurements on 512 SAs in an IC show the minimum required differential input voltage across the temperature range of 0 °C to 75 °C at 0.4 V is achieved to be 48% lower compared to CLSA and 28% lower compared to VLSA by both the DIBBSA-FL and DIBBSA-PD modes.

Identifying manufacturing defects in magnetic tunnel junction (MTJ) device is crucial for the yield and reliability of spin-torque-transfer (STT) magnetic random-access memory (MRAM) arrays. Several of the MTJ defects result inparametric deviations of the device that deteriorate over time. In this article, we present the design-for-testability (DFT) scheme for monitoring the electrical parameter deviations occurring due to the defect formation over time. A programmable DFT scheme was implemented for a subarray in 65-nm CMOS technology to evaluate the feasibility of the test scheme. The scheme utilizes the read sense path to compare the bit-cell electrical parameters against known DFT cell's characteristics. Built-in-self-test (BIST) methodology is utilized to trigger the onset of the fault once the device parameter crosses a threshold value. We demonstrate the operation and evaluate the accuracy of detection with the proposed scheme. The DFT scheme can be exploited for monitoring aging defects, modeling their behavior and optimization of the fabrication process.

We explore the idea of composing PUFs with the intent that the resultant PUF is stronger than the constituent PUFs. Prior work has proposed a construction, which subsequent work has shown to be weak. We revisit this prior construction and observe that it is actually weaker than previously thought when the constituent PUFs are arbiter PUFs. This weakness is demonstrated via our adaptation of the previously proposed Logistic Regression (LR) attack. We then propose new constructions called PUFs-composed-with-PUFs (PoP). In particular, we retain a two-layer construction, but allow the same input to the composite PUF to be input to more than one constituent PUF at the first layer. We explore this family of constructions, with arbiter PUFs serving as the constituent PUFs. In particular, we identify several axes which we can vary, and empirically study the resilience of our constructions compared to the prior construction and one another from the standpoint of LR attacks. As insight into why our family of constructions is stronger, we prove, under some idealized conditions, that the lower-bound on an attacker is indeed higher under our constructions than the upper-bound on an attacker for the prior construction. As such, our work suggests that composition can be a promising approach to strengthening PUFs, contrary to what prior work suggests.

Process control and yield of spin torque transfer-magnetoresistive random access memory (STT-MRAM) array are of crucial importance in fabrication. While yield depends on the CMOS process variability, quality of the deposited MTJ film, and other process nonidealities, test platform can enable a parametric optimization and verification process using the CMOS-based design-for-testability (DFT) circuits. In this paper, we develop a DFT algorithm and implement a DFT circuit for parametric testing and prequalification of the critical circuits in the CMOS wafer. The DFT circuit successfully replicates the electrical characteristics of MTJ devices and captures their spatial variation across the wafer with an error of less than 4%. We estimate the yield of the read sensing path by implementing the DFT circuit, which can replicate the resistance-area product variation up to 50% from its nominal value. The yield data from the read sensing path at different wafer locations are analyzed, and a usable wafer radius up to 75 mm has been estimated. Our DFT scheme can provide quantitative feedback based on in-die measurement, enabling fabrication process optimization through iterative estimation and verification of the calibrated parameters.

Variability in offset voltage, bitcell transistor conductance, and leakage currents can lead to marginal and intermittent failures in low-voltage SRAMs. In this paper, we develop a model of these marginal faults that includes such sense amplifier and bitcell variability. Using simulations and measurement data from a 65 nm test chip, we investigate the likelihood of these failures and propose how to stimulate their occurrence during testing.

We present a Discrete Cosine Transform (DCT) unit embedded with Error Detection Sequential (EDS) and Dynamic Voltage Scaling (DVS) circuits to speculatively monitor its noncritical datapaths. This monitoring strategy requires no buffer insertions with only minimal modifications to the existing digital design methodology and is therefore applicable for Field-Programmable Gate Array (FPGA) implementations. The proposed design is implemented in an FPGA. The duty cycles of the constraint clock and the actual clock are differentiated to guide the synthesizer to place the EDS circuits with specific timing margin. The proposed design is tested with two classic images and is able to detect timing errors in the noncritical datapaths due to dynamic process, voltage and temperature (PVT) variations. The DVS circuit correspondingly controls a linear voltage regulator to adjust the supply voltage to the Point of First Failure (PoFF). No actual timing errors are generated, primarily because of the unique speculative characteristic of the proposed monitoring strategy. Our proposed design incurs a 0.3% logic element overhead and 3.5% maximum frequency degradation. By lowering the supply voltage by 8.3%, the proposed design saves up to 16.5% energy when operating at the same frequency as a highly optimized baseline DCT implementation.

With a specified Mean Timing Between Failure (MTBF), the metastability resolution time of synchronizers possibly constrains the system performance. To enhance metastability resolution time under single low-voltage supply environments, Voltage-Boosted Synchronizers (VBSs) consisting of a basic minimum-sized Jamb latch and a switched-capacitor-based charge pump are proposed. The capacitor of the charge pump is sized 13 times the area of the Jamb latch. Two powering strategies of the charge pump, namely Metastability-driven VBS (MVBS) and Clock-driven VBS (CVBS), are proposed. For a 1-year MTBF specification, MVBS and CVBS show 2.0-2.7 and 5.1-9.8 times the performance improvement over the basic Jamb latch, respectively, without incurring large power consumption.

This work focuses on a multi-core VLSI implementation of a multiple-input multiple-output (MIMO) detector utilizing a sphere-decoding algorithm. A complex-domain node traversal algorithm that achieves similar performance results as that of an exhaustive-search algorithm where every node is checked and sorted is also described. A 4×4, 64-QAM hard-output detector utilizing this VLSI design occupies 98k gates, and achieves near-ML performance with an average throughput of 1.22 Gb/s and an energy/bit of 23 pJ/b on a nominal 1.2 V supply in a 0.13μm CMOS process. The hard-output design can be further expanded to provide soft-output capability, and achieves an average throughput of 0.65 Gb/s and reaches 10-5 BER at an SNR of 19.7 dB.

Power supply noise management continues to be a challenge with the scaling of CMOS technologies. Use of on-chip decoupling capacitors (decaps) is the most common noise suppression technique and has significant associated area and leakage costs. There are numerous methods of implementing decaps and it is not always clear which implementation is the most optimal for the given design constraints. This paper characterizes various decap implementations including MOS-based decaps, multilayer metal decaps, and metal-insulator-metal decaps using postlayout simulations in a 65-nm CMOS technology, and provides an outline for determining the most optimal selection and design of decaps based on area, leakage, and location. Hybrid structures are further shown to boost the area efficiency of conventional nMOS decaps by an additional${\sim}{25\%}$.

A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speedup of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64% (22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry lookahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.

A hybrid current/voltage sense amplification scheme is proposed for high speed SRAMs. The scheme includes an offset cancellation technique which makes it robust against the current sense amplifier (CSA) mismatch. The offset cancellation allows for fast open loop operation of the differential CSA. A fourfold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. Thanks to its automatic turn off nature, the proposed CSA incurs zero static power without an auxiliary turn off circuit. The reduction of the charge redistribution on the bitlines offers a low bitline dynamic power consumption as well. In this work, the proposed scheme is rigorously analyzed and compared to the conventional scheme. The analysis is verified using circuit level simulations and compared to the conventional scheme as a reference analytically and using simulations.

In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A ldquotiming windowrdquo technique is also proposed to reduce the amount of excessive power dissipation in the DFTL approach. A 64-bit Sklansky carry-merge adder is used as a benchmark comparison between different logic styles including DFTL, CDL, dynamic, and static logic. Simulation results reveal that the proposed work achieves better performance and is more energy efficient than the other logic styles for high performance adder designs.

Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.

Innovative architectural and circuit techniques are reducing the dynamic power in ternary content addressable memories (TCAMs). Also, shrinking device dimensions are making transistors increasingly leaky. Due to these two trends, the static power is becoming a significant portion of the total TCAM power. This paper presents two novel ternary storage cells that exploit the unique properties of TCAMs for reducing the cell leakage. Simulation results of the proposed cells show up to 40% leakage reduction over the conventional TCAM cell at the expense of a small degradation (<8%) in the static noise margin (SNM). The SNM degradation is negligible (<1%) for lower power supply voltages (<0.8 V). Measurement results of a test chip in 0.18-mum CMOS technology demonstrate that the proposed cells can perform read and write operations in less than 3.6 ns.

Fully digital analog to digital converters (FD-ADC) have potential applications in very low power ICs and can be implemented in digital CMOS technology. In this paper the non-linearity of the delay element (DE), which is the main building block in an FD-ADC, is discussed and its impact on the overall performance of the ADC is addressed. It is shown that the non-linearity of the delay element should be within certain limits in order to achieve the best signal to noise plus distortion ratio (SNDR). Also, a new current starved delay element with enhanced linearity is proposed. Using the proposed DE, the SNDR of a 6-bit FD-ADC is improved by 7dB.

In this paper a phase detector is introduced which has a similar phase detector response as the Alexander phase detector. Both the Alexander and proposed phase detector are analyzed with respect to their robustness. The analysis shows that the novel phase detector is more robust against process non-idealities than the Alexander, with a 75% reduction in the variation of static phase offsets. The proposed phase detector also consumes less power and requires less area. A CDR circuit which implements the proposed phase detector was designed and fabricated in a 0.18mum six metal layer standard CMOS process. The fabricated CDR circuit can lock to pseudo-random bit sequences (PRBS) up to 231-1 at data rates from 5 - 6.25Gb/s. For a PRBS of 231-1 at 6.25Gb/s the measured rms jitter and peak-to-peak jitter were 1.7ps and 11ps.

Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-mum technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16times16 bit multiplier

A new scheme to reduce the power consumption of static random access memories is presented. It is shown that using segmented virtual grounding (SVGND), it is possible to reduce both dynamic and static power consumption. The leakage power of the cells is reduced by reducing the voltage drop over a cell. The dynamic power dissipation is also reduced by eliminating the power consumption due to the discharge of the nondesired neighboring bitlines. The effectiveness of this scheme is compared to recently reported low-power schemes. It is shown that unlike those schemes, SVGND can accommodate multiple words in one row; a significant improvement in soft error rate tolerance

A PLL based frequency digitizer based on phase domain noise shaping is introduced. It is shown that the digitizer is a second order continuous time delta-sigma modulator operating in the phase domain. The proposed architecture is capable of digitizing the frequency of RF signals with a high degree of precision. This property can be used to digitize and demodulate an FM signal simultaneously. This concept is validated using a practical example based on a wireless standard. The simulation results exhibit a good agreement with the linear analysis. Moreover, benefits and drawbacks of this architecture are discussed and compared with respect to other architectures

A novel architecture for the reduction of both dynamic and static power consumption of static random access memories (SRAM) is presented. The scheme is based on the segmented virtual grounding (SVGND) of the SRAM cells. Substantial leakage reduction is achieved by increasing the threshold voltage of the cell transistors through body effect. The write and read energy consumptions are reduced significantly by decreasing the bitline voltage swing and the number of bitlines affected in each transaction. Unlike recently reported low-power schemes, SVGND allows multiple words to be placed in each row while keeping the dynamic power low. This feature is achieved by introducing an additional operation mode to the SRAM cells. The architecture is implemented in a 130nm CMOS technology. Using this scheme, the read and write array energy consumption can be saved by 44% and 84% respectively. Measurement results portraits 15 times leakage reduction compared to the conventional scheme.

In this paper, the application of dynamic threshold MOS (DTMOS) technique for low-voltage analog circuits is explored. The body terminal of PMOS transistors in bulk CMOS technology can be used as the forth terminal to enhance the performance of low-voltage analog circuits. To show the effectiveness of this technique, we have designed a continuous time common mode feedback (CMFB) circuit for a sub 1-V opamp and a new sub 1-V, 1-bit quantizer. A 0.8-V opamp with embedded CMFB and a 0.8-V, 1-bit quantizer for low-voltage DeltaSigma modulators are implemented in 0.18-mum CMOS technology. The simulation results as well as the measurement data of these blocks are presented in this paper

Ternary content addressable memories (TCAMs) are gaining importance in high-speed lookup-intensive applications. However, the high cost and power consumption are limiting their popularity and versatility. TCAM testing is also time consuming due to the complex integration of logic and memory. In this paper, we present a comprehensive review of the design techniques for low-power TCAMs. We also propose a novel test methodology for various TCAM components. The proposed test algorithms show significant improvement over the existing algorithms both in test complexity and fault coverage

Stability testing of SRAMs has been time consuming. This paper presents a new programmable DFT technique for detection of stability and data retention faults in SRAM cells. The proposed technique offers extended flexibility in setting the weak overwrite test stress, which allows to track process changes without time-consuming post-silicon design iterations. Moreover, it does not introduce extra circuitry in the SRAM array and surpasses the data retention test in test time and detection capability

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.

We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30 of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.

In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation. Our simulation results indicate that, for the 180nm-65nm CMOS technologies it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.

Conventional voltage scaling techniques rely on the characterization and monitoring of a unique critical path. However, the uniqueness of the critical path is a difficult requirement to establish in modern VLSI technologies due to the growing impact of process variations and interconnect parasitics on delay. This paper presents an on-chip critical path emulator architecture which tracks the changing critical path. The ability to emulate the actual critical path recovers most of the large margin added by conventional systems to guarantee a robust operation at all conditions. Due to the reduced margin, the proposed architecture is up to 45% and 21% more energy efficient compared to conventional open-loop and closed-loop voltage scaling systems respectively.

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. This has resulted in the design of multi-gigahertz microprocessors with unprecedented levels of integration. However, this is posing serious challenges to IC testing and long-term reliability. A major source of failures and test escapes in high performance ICs can be attributed to timing-only parametric failures. We implement a DFT technique to detect delay faults in a full custom 32-bit high performance ALU. We present the energy-delay tradeoffs and scaling trends associated with our DFT technique for the 180 nm-65 nm CMOS technologies. In addition, we demonstrate how this technique can be used to detect delay faults with improved resolution (/spl sim/60 ps for 180 nm technology) at relatively low, test mode clock frequencies.

SRAM cell stability has become an important design and test issue owing to significant process spreads, non-ideal operational conditions, and subtle manufacturing defects in scaled-down geometries. In this article, we carry out an extensive SRAM SNM sensitivity analysis and propose an SRAM cell stability fault model for weak cell detection. This fault model is used to design and verify a proposed digitally programmable design-for-test (DFT) technique targeting the weak cell detection in embedded SRAMs (eSRAM).

In this brief, we investigate the potential of reduced swing clock networks for low-power applications. We designed and laid out a full swing conventional and a reduced swing H-tree clock distribution network in 0.13-/spl mu/m CMOS technology operating at 500 MHz. In the reduced swing clock network, the swing was reduced in the global clock distribution network and was restored to the full swing in the local clock distribution domains. The post-layout simulation results of this research shows that a power saving of 22% under nominal operating condition is feasible.

This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5x increase in IOFF/mm per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor IOFF reduction and ION degradation due to each technique for the 130nm-70nm technologies. Our results indicate that the effectiveness of leakage control techniques and the associated energy vs. delay tradeoffs depend on the ratio of switching to leakage energies for a given technology. We use our findings to design a 70nm low power word line driver scheme for a 256 entry, 64-bit register file (RF). As a result, the leakage (total) energy of the word line drivers is reduced by 3x(2.5x) and for the RF by up to 35%(25%) respectively.

Burn-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45X/generation. This paper estimates the increase in junction temperature with scaling and discusses the optimal burn-in temperature with scaling. Our research indicates that the burn-in temperature must also be reduced with technology scaling. The impact on commercial burn-in ovens is also described. 1.

Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this paper, we carried out a transistor-level fault analysis and devise a search path test algorithm. The proposed algorithm is of the order (nl / log2n) compared to the brute-force algorithm of complexity (nl). For the analyzed CAM, the search path test complexity is reduced by 30x. 1.

This article presents a methodology for testing high-performance pipelined circuits with slow-speed testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. The technique adds no extra hardware in the data path of the pipeline and therefore has virtually no performance penalty. A clock timing circuit capable of achieving a timing resolution of 50 ps in 0.18 μm CMOS technology is presented. The design provides the ability to test the clock timing circuit itself. The effectiveness of the technique is demonstrated using a 16-bit pipelined multiplier as a test vehicle. Simulations show that we are able to detect delay faults as small as 50 ps at an input clock frequency of 100 MHz.

Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Although, a few types of digitally controlled delay elements have been proposed, an analytical expression for the delay of these circuits has not been reported. In this paper, we propose a new delay element architecture and develop an analytical equation for the output voltage and an empirical relation for the delay of the circuit. The proposed circuit exhibits improved delay characteristics over previously reported digitally controlled delay elements.

This paper presents a DFT (design-for-testability) technique for delay fault testing of high performance, dynamic CMOS circuits. A high performance, delay fault testable, 16 bit adder is designed in 0.18 /spl mu/m CMOS technology. Simulations for the adder demonstrate that this technique can detect delay faults greater than 35 ps and improves delay fault detection capability. It also allows at least 10/spl times/ reduction in test mode clock frequency. Furthermore, the proposed method is capable of providing delay fault diagnostics. However, the proposed DFT technique increases delay by 8.6% with minimal power penalty.

The clock frequency of high performance VLSIs has exceeded 2 GHz. Over the years, aggressive scaling of CMOS process technology has resulted in a 30% annual performance improvement for digital circuits. However, tester speed has improved by only 12% every year. This paper discusses various test methodologies being used to cope with this speed disparity. These include: very low voltage test techniques; DFT structure incorporation; low frequency test modes; and dynamic CMOS implementations with integrated test mode structures.

This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-power applications. For each DETFF, the optimal delay, power consumption, and power-delay product are determined as the primary figures of merit. The proposed design is shown to have the least energy at low voltages.

Article Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors Share on Authors: James Tschanz Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Siva Narendra Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Zhanping Chen Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Shekhar Borkar Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Manoj Sachdev Department of ECE, University of Waterloo, Canada Department of ECE, University of Waterloo, CanadaView Profile , Vivek De Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 147–152https://doi.org/10.1145/383082.383121Online:06 August 2001Publication History 39citation804DownloadsMetricsTotal Citations39Total Downloads804Last 12 Months50Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This paper presents a methodology for testing high performance circuits with a low-speed clock in test mode. Using this technique, the frequency of the 50% duty cycle test mode clock can be reduced with virtually no lower limit. This poses very little requirements on automatic test equipment (ATE) and facilitates the testing process. A CMOS implementation that achieves 50 ps accuracy is also presented. This technique targets designs using design for testability (DFT) and/or built-in self test (BIST) techniques.

Technology scaling challenges the effectiveness of current-based test techniques such as I/sub DDQ/. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I/sub DDQ/ versus F/sub MAX/ (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, I/sub DDQ/ versus temperature test can be deployed. Our data show that temperature (cooling from 110/spl deg/C to room) improved sensitivity of I/sub DDQ/ Versus F/sub MAX/ two-parameter test by more than an order of magnitude (13.8X). The sensitivity can also be tuned by proper selection of a temperature range to match a required DPM level.

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed.

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. In addition, various implementations aspects of this technique are addressed.

Transient current testing (I/sub DDT/) has been often cited as an alternative and/or supplement to I/sub DDQ/ testing. In this article we investigate the potential of transient current testing in faulty, chip detection with silicon devices. The effectiveness of the I/sub DDT/ test method is compared with I/sub DDQ/ as well as with SA-based voltage testing. Photon emission microscopy is used to localize defects in several faulty, devices. Furthermore, the potential of I/sub DDT/ testing for leaky deep sub-micron devices is investigated.

The problem of pass/fail decision making with I/sub DDQ/ testing will become increasingly difficult as the feature size and voltage are reduced in deep sub-micron regions due to increased transistor sub-threshold leakage currents. The off current of minimum sized devices is expected to increase at least by a factor of 100 as the feature size is reduced from 0.5 micron to 0.1 micron. The increase in transistor off current with ULSI complexity will have a significant impact on the future ofI/sub DDQ/ testing.

The controllability condition in sequential circuits is not enough for I/sub DDQ/ detection of a class of bridging faults. Special DfT measures are needed to detect such bridging faults by I/sub DDQ/ test technique. In this article, we propose two flip-flop configurations which are inherently I/sub DDQ/ as well as voltage testable. Therefore, in these configurations, the controllability condition is sufficient for I/sub DDQ/ testing of bridging faults and need for special DfT measures is no longer required. An additional inverter is needed to change popular master-slave flip-flop configurations into these configurations. The I/sub DDQ/ test strategy and timing impact of the modification are also examined.

Inductive Fault Analysis (IFA) for analog circuits has received considerable attention in recent years. IFA can be exploited for simplifying various aspects of analog testing. It can also be exploited towards design robustness against process defects, fault grading of a design and examining practicality of analog DfT schemes. In this article, we analyse both aspects of analog IFA with real life examples. Towards the test side, the simulated as well as silicon data demonstrate the strengths of IFA based test methods in test cost reduction and structural test generation. However, some of the escaped devices suggest partial specification testing along with IFA based test is desirable from a quality as well as economic point of view. Towards the design side, the simulation results highlight macros where DfT is needed most and help in determination of effective DfT schemes.

Embedded DRAMs are an integral part of modern ICs. Owing to limited accessibility, the testing of embedded memories is a time consuming exercise. Such memories designed in a standard VLSI process show susceptibility to catastrophic as well as non-catastrophic defects. Taking into account catastrophic and non-catastrophic defects, an accurate and efficient fault model has been developed. Using this fault model linear test algorithms of complexity 8N and 9N have been developed.>