In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

Since only sensitizable paths contribute to the delay of a circuit, false paths must be excluded in optimizing the delay of the circuit. However, just identifying sensitizable paths in the first place is not sufficient since during the optimization process, false paths may become sensitizable, and sensitizable paths false. In addition, some paths may shuttle frequently as false paths and sensitizable ones. That is, a thrashing phenomenon may occur. To lessen the thrashing phenomenon of critical paths, a loose sensitization criterion is proposed in this paper to identify both exact sensitizable paths and shuttle paths. Moreover, the selection of sensitization criterion should be related to the specified delay constraint of a given circuit. Taking into account the tightness of sensitization criterion and delay constraint together, we define in this paper a thrashing coefficient which is used to guide the selection of sensitization criterion in the performance optimization process. Moreover, to save time for path sensitizability analysis in the optimization process, we find a special type of false paths, function-false paths, which can be put aside since they never become sensitizable during the process.

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Since only sensitizable paths contribute to the delay of a circuit, false paths must be excluded in optimizing the delay of the circuit. Just identifying false paths in the first place is not sufficient since during iterative optimization process, false paths may become sensitizable, and sensitizable paths false. In this paper, we examine cases for false path becoming sensitizable and sensitizable becoming false. Based on these conditions, we adopt a so-called loose sensitization criterion which is used to develop an algorithm for dynamically identification of sensitizable paths. By combining gate sizing and dynamically identification of sensitizable paths, an efficient performance optimization tool is developed. Results on a set of circuits from ISCAS benchmark set demonstrate that our tool is indeed very effective in reducing circuit delay with less number of gate sized as compared with other methods.