Specifications for complex designs and their consistency are always a headache. Automated specification mining - including but not limited to generative AI - offers attractive solutions, but there are also various unmet needs.

Dear Colleagues, Welcome to the 58thDesign Automation Conference, and welcome back to the beautiful city by the bay— San Francisco! DAC has always been a unique event and this year is no exception. After all, DAC is the only event that brings together the entire design and design automation ecosystem, which includes academic and industrial researchers, electronic executives and managers, IC and systems designers and developers, educators, and of course vendors.

Technical publications often make either subjective or unsubstantiated claims about today's functional verification process---such as, 70 percent of a project's overall effort is spent in verification. Yet, there are very few credible industry studies that quantitatively provide insight into the functional verification process in terms of verification technology adoption, effort, and effectiveness. To address this dearth of knowledge, a recent world-wide, double-blind, functional verification study was conducted, covering all electronic industry market segments. To our knowledge, this is the largest independent functional verification study ever conducted. This paper presents the findings from our 2014 study and provides invaluable insight into the state of the electronic industry today in terms of both design and verification trends.

In 1997, SEMATECH set off an alarm in the industry when it warned that productivity gains related to IC manufacturing capabilities (which increased at about 40% per year) outpaced the productivity gains in IC design capabilities (which increased at about 20% per year). In spite of this alarming gap between growing silicon capacity and design capabilities, the industry never felt the effects. Why? This invited talk reviews the findings from the 2012 Wilson Research Group Functional Verification Study and identifies the trends that prevented the design productivity gap. However, a more ominous challenge than the design productivity gap is emerging. While silicon capacity grows at a Moore's Law rate, verification effort grows at a double exponential rate, and the solutions used to close the design productivity gap will not be sufficient to close the verification productivity gap. This invited talk concludes with a discussion on the changes needed to overcome the verification productivity gap.

Post-silicon validation is a necessary step in a design's verification process. Pre-silicon techniques such as simulation and emulation are limited in scope and volume as compared to what can be achieved on the silicon itself. Some parts of the verification, such as full-system functional verification, cannot be practically covered with current pre-silicon technologies. This panel brings together experts from industry, academia, and EDA to review the differences and similarities between pre- and post-silicon, discuss how the fundamental aspects of verification are affected by these differences, and explore how the gaps between the two worlds can be bridged.

Success of simulation-based functional verification depends on the quality and diversity of the verification tests that are simulated. The objective of test generation methods is to generate tests that exercise as much different functionality of the hardware designs as possible. In this paper, we propose a novel methodology that generates a model of the verification tests in a given test set using unsupervised support vector analysis. One potential application is to use this model to select tests that are likely to exercise functionality that has not been tested so far. Since this selection can be done before simulation, it can be used to filter redundant tests and reduce required simulation cycles. Our methodology can be combined with a test generation method like constrained-random test generation to increase its effectiveness without making fundamental changes to the verification flow. Experimental results based on application of the proposed methodology to the OpenSparc T1 processor are reported to demonstrate the practicality of our approach.

Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverage metrics are essential to guide the development of effective test suites. Traditional coverage metrics are defined based on either a functional model or a structural model of the design. If our goal is to select a subset of tests from a set of tests, using these coverage metrics require simulation of the entire set before the effectiveness of tests can be compared. In this paper, we propose a novel methodology that estimates the input space covered by a set of tests. We use unsupervised support vector analysis to learn such a space, resulting in a subset of tests that represent the original set of tests. A direct application of this methodology is to select tests before simulation in order to reduce simulation cycles. Consequently, simulation effectiveness can be improved. Experimental results based on application of the proposed methodology to the OpenSparc T1 processor are reported to demonstrate the practicality of our approach.

No abstract available.

Few would disagree that verification takes the lion's share of today's project resources. If we examine the available research, we quickly discover that verification is a significant pain point that consumes massive amounts of time and resources across a multitude of market segments. Per Gary Smith at Gartner Dataquest, verification consumes 30% to 70% of total schedule, depending on design size. According to Collett International Research, Inc., a majority of ASICs and integrated circuits (ICs) require at least one respin with 71% of respins are due to functional bugs "verification should have caught".With such statistics, it is easy to understand why many contend that the verification challenge is growing at a double exponential rate (that is, exponential with respect to Moore's law). Given verification's importance and its significant impact on fundamental design quality and time-to-market demands, what is our industry doing in response? This panel explores where the methodology highway is taking us - is the destination heaven or just another level of Dante's inferno?Respected authors and experts in verification methodology will share their insights and opinions of the two methodologies used today: verify-after-the-fact (traditional) and verify-as-you-design (emerging). For decades, simulation has necessitated a verify-after-the-fact methodology and yet we can see from the industry research that a high percentage of silicon requires respins. With the latest advances in simulation testbenches and languages, can the verify-after-the-fact approach scale? Or, is it time for a move to a higher level of abstraction that enables a verify-as-you-design methodology.Industry leading chip and systems companies will discuss the methodologies they employ today to address the enormous challenge of functional verification. Questions to be addressed by our esteemed panelists include: How can we bring in schedules? What can we do to increase design quality? What cultural and organizational changes have to take place to bring quality back to the forefront of design? Where is the measurable proof of quality? What are the questions that managers should be asking themselves? What are the engines being used? What formal techniques deliver the greatest success? How important is HW/SW verification? What are the processes or methodologies being used to overcome tool or technology limitations? What is the value of assertions? How does a geographically dispersed engineering team impact design quality? What are the metrics being used to measure progress and success? And how do you know when you are done?Today we currently don't design quality in - we TEST it in (using simulation). But, what would happen if quality was designed in from the beginning? How much could we improve the overall quality level and reduce verification time, and what would this take to do it? Finally, can migration to a new methodology be the highway out of verification hell?

Summary form only given. With the ever increasing growth of size and complexity of digital designs, tools have just kept pace. Design engineers bare the brunt of the problem. To make use of dynamic verification, designers invest as much or more time into their testbenches as they do in the design they are creating. For static or formal verification, large designs with complex state spaces have challenged even the most powerful formal tools. What changes are coming in the design and EDA spaces that will improve this situation? What is the right mix of dynamic and static verification for the future?.

Do formal verification tools and methodologies require a drastic overhaul to move beyond equivalence checking? Equivalence checking catches errors in synthesis and local hand-modifications to designs. However, powerful formal verification technologies are emerging to combat "behavioral" errors, which represent today's biggest verification problems. Nonetheless, formal verification experts are split on how formal tools should adapt to this challenge. Some of our panelists feel that designers can sufficiently benefit from new formal verification technologies by making incremental changes to current methodologies. Others, however, argue that major changes are required to reap meaningful benefits from these new technologies. Just how much change is enough, what is the capacity of our current tools and what is limiting the full deployment of FV technology.Our panel of experts, consisting of users, tool providers, and core engine builders, will answer these challenging questions. The panel will debate these issues while discussing real life examples from the user base. They will provide a perspective of how the progression of technology will bring the real promise of formal verification to the user base.