Blockchain scalability is an active area of research. One of the promising approaches is the execute-order-validate (X-O-V) blockchain architecture, which leverages high concurrency. Meanwhile, many transactions exhibit dynamic locality—a workload characteristic with a high degree of locality that changes over time (e.g., due to the mobility of devices). In this article, we propose DyloChain, a hierarchical blockchain supporting dynamic locality by extending the X-O-V architecture across sharding zones. In DyloChain’s hierarchy, higher-level servers (called M-nodes) are responsible for cross-zone communication with a main chain to ensure global consistency and availability, while lower-level servers (called L-nodes) validate local blocks with a local chain. To support dynamic locality, DyloChain suggests an order-execute-order-validate (O-X-O-V) transaction processing model that extends the X-O-V model to accommodate the hierarchical structure. Specifically, the O-X-O-V model optimizes efficiency through speculative local updates on each local chain (O-X) for the early removal of potential conflicts within a zone and enables high parallelism across zones. Subsequently, the model aggregates these local blocks onto the main chain (O-V), ensuring a globally consistent total order across zones. This is facilitated by an extended validation procedure that detects interferences between concurrently dependent transactions across zones. DyloChain resolves interferences using a state synchronization protocol that synchronizes the corresponding main states of the interfered local states into the involved local chains. DyloChain improves locality by employing a state reshard protocol that transfers a user’s state ownership between source and destination local chains by atomically committing user-issued reshard requests to the involved chains. We implement and conduct comprehensive performance evaluations of DyloChain under various configurations.

Proof-of-Authority (PoA) is one of the popular blockchain consensus protocols, particularly for permissioned blockchains. However, PoA (as in Clique) still faces performance scalability issues. Its leader-based design restricts throughput and results in resource inefficiency, as it permits only one block to be accepted in each round, discarding all other concurrently proposed blocks in the same round. In this paper, we introduce DaPoA, an effort to enhance the Ethereum PoA Clique network to improve its performance scalability. The main idea of DaPoA is that it follows a parallel leader architecture that allows multiple sealers to propose their blocks in each round, which are then accepted in the same round. To achieve this, DaPoA employs a state-of-the-art directed acyclic graph (DAG)-based Byzantine Fault Tolerant (BFT) consensus algorithm, which enables parallel block proposals for high scalability with leader-less design. We have implemented and evaluated DaPoA on top of the Ethereum PoA Clique to demonstrate its performance scalability. In our setting of eight nodes, DaPoA achieves a 2.47 x higher throughput and 5.76x lower latency compared to Clique.

The primary bottleneck of blockchain is shifting from consensus to execution due to recent advances in DAGbased consensus algorithms supporting over 100k TPS. Many blockchain systems segregate execution from ordering, missing the opportunity to harness potential parallelism in consensusproduced batches. In this paper, we propose a new deterministically orderable concurrency control algorithm, OptME, which improves the performance of execution phase by exploiting inherent parallelism among transactions. This algorithm analyzes transaction dependencies to extract parallelism, and determines the total order of transaction execution. OptME consists of three steps: (1) building a transaction dependency graph, (2) generating a parallel execution schedule, and (3) executing transactions based on the schedule. We employ several optimizations, including parallel dependency graph construction, early abort detection, and efficient reordering with an optimistic assumption. Our evaluation demonstrates that OptME achieves up to 350k TPS and outperforms a state-of-the-art concurrency control algorithm, even under high contention scenarios.

Business is innovating with the advent of blockchain that tokenizes digital assets. To expand the blockchain's potential, Ethereum, a representative permissionless blockchain platform, supports the fungible token (FT) standard ERC-20 and the nonfungible token (NFT) standard ERC-721. Hyperledger Fabric (Fabric), a representative permissioned blockchain platform, proposed FabToken to support tokens in version 2.0.0 alpha. But FabToken contains only FTs, not NFTs. Given the market share in the enterprise blockchains, Fabric needs to support NFTs as soon as possible. This paper presents a unique digital asset management system called FabAsset so that Fabric can run decentralized applications that require NFTs. This paper describes the design of FabAsset, consisting of chaincode and SDK (Software Development Kit), and the prototype of a decentralized signature service leveraging FabAsset to validate its usefulness.

Many Blockchain-as-a-Service (BaaS) providers have emerged with the growing interest in BaaS among enterprises. However, current BaaS providers can pose a potential security threat in the context of a centralized service provider and for clients that depend on the provider. In this study, we first consider the problem of auditing BaaS and develop an Enforcer architecture for trustworthy BaaS.

Phase-change RAM (PRAM) is a promising candidate of emerging memory technologies which provides large capacity and low leakage power to compensate for the limitations of DRAM in the hybrid DRAM/PRAM memory subsystem. However, for practical applications of PRAM in the hybrid main memory, we need to reduce write traffics to PRAM in order to overcome the write-related limitations in PRAM such as write endurance. In our work, we propose a concept called in-DRAM write buffer for the hybrid main memory to reduce PRAM write traffics. The cache line-level dirty data are filtered out from the evicted DRAM row and stored in the write buffer which occupies a portion of DRAM by sacrificing the capacity of DRAM cache. In order to reduce PRAM writes, the write buffer tries to maximize write coalescing by avoiding the PRAM write-back of soon-to-be-accessed dirty data. In order to adapt to the dynamically changing program behavior in PRAM writes, we also propose a method to adjust the write buffer size dynamically during runtime. Experimental results show that the proposed dynamic method offers up to 91.92% reduction in PRAM writes and gives results (average 14.81% and 9.47% reduction in PRAM writes and program runtime, respectively) comparable to the best of static write buffer size cases.

This paper introduces the notion of intelligent SSDs. First, we present the design considerations of intelligent SSDs, and then examine their potential benefits under various settings in data mining applications.

Intelligent solid-state drives (iSSDs) allow execution of limited application functions (e.g., data filtering or aggregation)on their internal hardware resources, exploiting SSD characteristics and trends to provide large and growing performance and energy efficiency benefits. Most notably, internal flash media bandwidth can be significantly (2-4x or more) higher than the external bandwidth with which the SSD is connected to a host system, and the higher internal bandwidth can be exploited within an iSSD. Also, SSD bandwidth is projected to increase rapidly over time, creating a substantial energy cost for streaming of data to an external CPU for processing, which can be avoided via iSSD processing. This paper makes a case for iSSDs by detailing these trends, quantifying the potential benefifits across a range of application activities, describing how SSD architectures could be extended cost-effectively, and demonstrating the concept with measurements of a prototype iSSD running simple data scan functions. Our analyses indicate that, with less than a 2% increase in hardware cost over a traditional SSD, an iSSD can provide 2-4x performance increases and 5-27x energy efficiency gains for a range of data-intensive computations.

This paper explores the benefits and limitations of in-storage processing on current Solid-State Disk (SSD) architectures. While disk-based in-storage processing has not been widely adopted, due to the characteristics of hard disks, modern SSDs provide high performance on concurrent random writes, and have powerful processors, memory, and multiple I/O channels to flash memory, enabling in-storage processing with almost no hardware changes. In addition, offloading I/O tasks allows a host system to fully utilize devices' internal parallelism without knowing the details of their hardware configurations. To leverage the enhanced data processing capabilities of modern SSDs, we introduce the Smart SSD model, which pairs in-device processing with a powerful host system capable of handling data-oriented tasks without modifying operating system code. By isolating the data traffic within the device, this model promises low energy consumption, high parallelism, low host memory footprint and better performance. To demonstrate these capabilities, we constructed a prototype implementing this model on a real SATA-based SSD. Our system uses an object-based protocol for low-level communication with the host, and extends the Hadoop MapReduce framework to support a Smart SSD. Our experiments show that total energy consumption is reduced by 50% due to the low-power processing inside a Smart SSD. Moreover, a system with a Smart SSD can outperform host-side processing by a factor of two or three by efficiently utilizing internal parallelism when applications have light trafic to the device DRAM under the current architecture.

The notion of object-based storage devices (OSDs) has been proposed to overcome the limitations of the traditional block-level interface which hinders the development of intelligent storage devices. The main idea of OSD is to virtualize the physical storage into a pool of objects and offload the burden of space management into the storage device. We explore the possibility of adopting this idea for solid state drives (SSDs). The proposed object-based SSDs (OSSDs) allow more efficient management of the underlying flash storage, by utilizing object-aware data placement, hot/cold data separation, and QoS support for prioritized objects. We propose the software stack of OSSDs and implement an OSSD prototype using an iSCSI-based embedded storage device. Our evaluations with various scenarios show the potential benefits of the OSSD architecture.

Data storage devices are getting "smarter." Smart Flash storage devices (a.k.a. "Smart SSD") are on the horizon and will package CPU processing and DRAM storage inside a Smart SSD, and make that available to run user programs inside a Smart SSD. The focus of this paper is on exploring the opportunities and challenges associated with exploiting this functionality of Smart SSDs for relational analytic query processing. We have implemented an initial prototype of Microsoft SQL Server running on a Samsung Smart SSD. Our results demonstrate that significant performance and energy gains can be achieved by pushing selected query processing components inside the Smart SSDs. We also identify various changes that SSD device manufacturers can make to increase the benefits of using Smart SSDs for data processing applications, and also suggest possible research opportunities for the database community.

Using the cloud storage services, users can access their data in any time, at any place, even with any computing device including mobile devices. Although these properties provide flexibility and scalability in handling data, security issues should be handled especially when mobile devices try to access data stored in cloud storage. Currently, a typical cloud storage service, Dropbox, offers server-side data encryption for security purpose. However, we think such method is not secure enough because all the encryption keys are managed by software and there is no attestation on the client software integrity. Moreover, a simple user identification based on user ID and Password is also easy to be compromised. Data sharing which is critical in enterprise environment is significantly restricted because it is not easy to share encryption key among users. In this paper, we propose DFCloud, a secure data access control method of cloud storage services to handle these problems found in the typical cloud storage service Dropbox. DFCloud relies on Trusted Platform Module (TPM) [1] to manage all the encryption keys and define a key sharing protocol among legal users. We assume that each client is mobile device using ARM TrustZone [2] technology. The DFCloud server prototype is implemented using ARM Fastmodel 7.1 and Open Virtualization software stack for ARM TrustZone. For DFCloud client, TPM functions are developed in the secure domain of ARM TrustZone because most ARM-based mobile devices are not equipped with TPM chip. The DFCloud framework defines TPM-based secure channel setup, TPM-based key management, remote client attestation, and a secure key share protocol across multiple users/devices. It is shown that our concept works correctly through a prototype implementation.

In this paper, we propose a fast and simple system emulator, called a system performance emulator (SPE), to evaluate long read operations. The SPE estimates how much system-wide performance is enhanced by using a faster solid state disk (SSD). By suspending a CPU for a certain time during direct memory access (DMA) transfer and subtracting this suspended time from the total DMA time, the SPE estimates the improvement in system performance expected from an enhanced SSD prior to its manufacture. We also examine the relation between storage performance and system performance using the SPE.

The problem of accessing and managing digital contents scattered on personal portable devices such as smart phone, digital camera, MP3 player, or laptop in an integrated fashion is critical in ubiquitous computing. It is not trivially solvable because the underlying networks are dynamically configured and the data types supported by each device are constrained. Due to recent rapid growth in personal digital contents, it becomes a major issue. To address this challenge, we have proposed a self-managed distributed file services called PosCFS+ in personal area networks (PAN). PosCFS+ automatically detects every device available in PAN and integrates the storage space of all the devices into a virtual storage. In order to facilitate data access to the virtual storage, PosCFS+ creates virtual directories which enable a semantic file addressing from applications. However, in a real world consisting of multiple consumer electronics (CE) devices, it is not easy or even impossible to install software components like PosCFS+ in the CE devices because they are proprietary. In this paper, we present the design and implementation of a CE device agent which enables the storage virtualization by PosCFS+ on CE device ensembles. Most CE devices are connected to a host computer via USB interface, so the agent will be executed on the host computer to export the physical storage space of a CE device to PosCFS+. Then, virtual storages and virtual directories are created by PosCFS+ according to predefined user profile. Finally, to solve the problem of limited data type and format supported in a CE device, the event notification framework proposed is used for automatic data transcoding.

The past few decades have witnessed a chronic and widening imbalance among processor bandwidth, disk capacity, and access speed of disk. According to Amdhal's law, the performance enhancement possible with a given improvement is limited by the amount that the improved feature is used. This implies that the performance enhancement of an OLTP system would be seriously limited without a considerable improvement in I/O throughput. Since the market debut of flash memory SSD a few years ago, we have made a continued effort to overcome its poor random write performance and to provide stable and sufficient I/O bandwidth. In this paper, we present three different flash memory SSD models prototyped recently by Samsung Electronics. We then show how the flash memory SSD technology has advanced to reverse the widening trend of performance gap between processors and storage devices. We also demonstrate that even a single flash memory drive can outperform a level-0 RAID with eight enterprise class 15k-RPM disk drives with respect to transaction throughput, cost effectiveness and energy consumption.

In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploration of such systems needs to explore a wide design space spanned by detailed architecture parameters through cycle-accurate performance estimation. For fast exploration, the proposed methodology is based on an efficient evolutionary algorithm, called QEA, and trace-driven simulation to evaluate architecture candidates quickly. We applied the proposed methodology to NAND flash-based Multimedia Card as a case study considering the following design parameters: buffer size, flash memory configuration, clock, communication architecture, and memory allocation. The experimental results validate the proposed methodology by showing the optimal architecture configurations with varying performance constraints and design parameters.

Due to its superiority such as low access latency, low energy consumption, light weight, and shock resistance, the success of flash memory as a storage alternative for mobile computing devices has been steadily expanded into personal computer and enterprise server markets with ever increasing capacity of its storage. However, since flash memory exhibits poor performance for small-to-moderate sized writes requested in a random order, existing database systems may not be able to take full advantage of flash memory without elaborate flash-aware data structures and algorithms. The objective of this work is to understand the applicability and potential impact that flash memory SSD (Solid State Drive) has for certain type of storage spaces of a database server where sequential writes and random reads are prevalent. We show empirically that up to more than an order of magnitude improvement can be achieved in transaction processing by replacing magnetic disk with flash memory SSD for transaction log, rollback segments, and temporary table spaces.

New fusion memory devices consisting of multiple heterogeneous memory components in a single die or package offer efficient ways to optimize embedded systems in terms of energy, performance, and cost. Samsung Electronics recently announced the OneNAND fusion memory, in which a NAND flash array is integrated with dual SRAM buffers to provide a nor-type I/O interface. OneNAND has the low cost and large capacity of a NAND flash but also permits eXecution-in-Place (XIP) like a nor flash. The deployment of such devices requires careful system-level resource management because of their impact on energy consumption and performance, and existing memory optimization techniques, such as the demand paging used with NAND flash, may no longer be appropriate for systems with a fusion memory. We introduce a new online demand paging scheme that fully exploits the XIP capability of OneNAND flash by classifying pages as load preferred (residing in the on-chip SRAM) and XIP preferred (accessed directly from the OneNAND flash and discarded after use). This achieves, on average, a 26% reduction in energy consumption and a 19% increase in performance, compared with conventional NAND flash demand paging.

In this article, a novel FTL (flash translation layer) architecture is proposed for NAND flash-based applications such as MP3 players, DSCs (digital still cameras) and SSDs (solid-state drives). Although the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, efficient algorithms of an FTL have a significant impact on performance as well as the lifetime. After the dominant parameters that affect the performance and endurance are categorized, the design space of the FTL architecture is explored based on a diverse workload analysis. With the proposed FTL architectural framework, it is possible to decide which configuration of FTL mapping parameters yields the best performance, depending on the differing characteristics of various NAND flash-based applications.

In this paper, we propose a novel, application specific demand paging mechanism for low-end embedded systems with flash memory as secondary storage. These systems are not equipped with virtual memory. A small memory space called an execution buffer is allocated to page an application. An application-specific page manager manages the buffer. The manager is generated by a compiler post-pass and combined with the application image. Our compiler post-pass analyzes the ELF executable image of an application and transforms function call/return instructions into calls to the page manager. As a result, each function of the code can be loaded into memory on demand at run time. To minimize the overhead of demand paging, code clustering algorithms are also presented. We evaluate our techniques with five embedded applications. We show that our approach can reduce the code memory size by 33% on average with reasonable performance degradation (8-20%) and energy consumption (10% more on average) for low-end embedded systems.

The ever-increasing requirement for high-performance and huge-capacity memories of emerging embedded applications has led to the widespread adoption of SDRAM and NAND flash memory as main and secondary memories, respectively. In particular, the use of energy consuming memory, SDRAM, has become burdensome in battery-powered embedded systems. Intuitively, though demand paging can be used to mitigate the increasing requirement of main memory size, its applicability should be deliberately elaborated since NAND flash memory has asymmetric operation characteristics in terms of performance and energy consumption.In this paper, we present energy-aware demand paging technique to lower the energy consumption of embedded systems considering the characteristics of interactive embedded applications with large memory footprints. We also propose a flash memory-aware page replacement policy that can reduce the number of write and erase operations in NAND flash memory. With real-life workloads, we show the system-wide Energy·Delay can be reduced by 15~30% compared to the traditional shadowing architecture.

Memory system is a major performance and power bottleneck in embedded systems especially for multimedia applications. Most multimedia applications access stream type of data structures with regular access patterns. It is observed that conventional caches behave poorly for stream-type data structure. Therefore, prediction-based prefetching techniques have been extensively researched to exploit the regular access patterns. Prefetching, however, may pollute the cache if the prediction is not accurate and needs extra hardware prediction logic. To overcome these problems, we propose a novel hardware prefetching technique that is assisted by static analysis of data access pattern with stream caches. With the proposed stream cache architecture, we could achieve significant performance improvement compared with the conventional cache architecture.

NAND flash memory has become an Indispensable component in embedded systems because of its versatile features such as nonvolatility, solid-state reliability, low cost and high density. Even though NAND flash memory gains popularity as data storage, it also can be exploited as code memory for XIP (execute-in-place). We present a cost-efficient memory architecture, which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the proposed approach is demonstrated with real embedded workloads on a real hardware prototyping board.

The high-low water mark destage (HLWM) algorithm is widely used to enable a cached RAID5 to flush dirty data from its write cache to disks. It activates and deactivates a destaging process based on two time-invariant thresholds which are determined by cache occupancy levels. However the opportunity exists to improve I/O throughput by adaptively changing the thresholds. This paper proposes an adaptive HLWM algorithm which dynamically changes its thresholds according to a varying I/O workload. Two thresholds are defined as the multiplication of changing rates of the cache occupancy level and the time required to fill and empty the cache. Performance evaluations with a cached RAID5 simulator reveal that the proposed algorithm outperforms the HLWM algorithm in terms of read response time, write cache hit ratio, and disk utilization.

Abstract- 3D graphics is becoming an important application area together with multimedia applications. The dynamic behavior of 3D graphics application brings new challenges for system level specification and synthesis methodologies. Although existing dataflow models are successfully used for DSP system design, they are not sufficient to deal with 3D graphics algorithms since they lack in global state management and dynamic behavior handling. In this paper, we propose an extended synchronous piggybacked dataflow model with dynamic constructs for representing 3D graphics algorithm. We also present implementation techniques for software and hardware synthesis from the specification. With a simple 3D graphics pipeline, we show the novelty and usefulness of the proposed specification model. I.

Multimedia applications are an increasingly important workload for general-purpose processors. This paper analyzes frame-level execution time variability for several multimedia applications on general-purpose architectures. There are two reasons for such an analysis. First, it has been conjectured that complex features of such architectures (e.g., out-of-order issue) result in unpredictable execution times, making them unsuitable for meeting real-time requirements of multimedia applications. Our analysis tests this conjecture. Second, such an analysis can be used to effectively employ recently proposed adaptive architectures.