A method for analyzing the functional behavior and the performance of programs in distributed systems is presented. We use hybrid monitoring, a technique which combines advantages of both software monitoring and hardware monitoring. The paper contains a description of a hardware monitor and a software package (ZM4/SIMPLE) which make our concepts available to programmers, assisting them in debugging and tuning of their code. A short survey of related monitor systems highlights the distinguishing features of our implementation. As an application of our monitoring and evaluation system, the analysis of a parallel ray tracing program running on the SUPRENUM multiprocessor is described. It is shown that monitoring and modeling both rely on a common abstraction of a system's dynamic behavior and therefore can be integrated to one comprehensive methodology. This methodology is supported by a set of tools.>

The evolution of technology provides the opportunity of forming large processor ensembles working closely together. When decomposing application programs and assigning subtasks to different processors we expect not only high throughput, but also the fastest possible execution of each individual demand. The level of performance in these areas is strongly influenced by the hardware interconnection structure and by the communication software.

The contemporary general purpose computer of the Princeton type is limited in its performance by the speed of the available logic families. Many projects around the world try to achieve higher performance by using many processors connected via common memories. The hardware costs for the interconnection of many processors and memories has to be limited and a severe degradation resulting from memory access conflicts must be avoided. The EGPA-project uses the concept of restricted neighbourhoods to solve these problems. The processors and memories are arranged in a freely extensible cellular structure. The number of connections to processors and to memories are limited for all sizes of the array. In this paper we present measured results from the pilot system, which show whether memory conflicts will influence the speed of the individual processors. The results will be valid for larger arrays, too.