Age prediction for integrated circuits (ICs) is essential in establishing prevention and mitigation steps to avoid unexpected circuit failures in the field. Any electronic system would get benefit from an accurate age calculation. Additionally, it would assist in reducing the amount of electronic waste and the effort toward green computing. In this article, we propose a methodology to estimate the age of ICs using the Gaussian process regression (GPR). The output frequency of the ring oscillator (RO) is influenced by various factors, including the trackable path, voltage, temperature, and ageing. These dependencies are leveraged in the GPR model training. We demonstrate the RO’s frequency degradation by employing the Synopsys HSPICE tool with 32 nm predictive technology model (PTM) and the Synopsys technology library. We used temperature variation from 0 °C to 100 °C and voltage variation from 0.80 to 1.05 V for the data acquisition. Our methodology predicts age precisely; the minimum prediction accuracy with a month deviation on linear sampling rate is 85.36% for 13-Stage RO and 87.09% for 21-Stage RO, with a range of improvement in prediction accuracy compared to state-of-the-art (SOTA) is 9.74% to 16.99%. Similarly, on the logarithmic sampling rate, the prediction accuracy for 13-Stage RO and 21-Stage RO are 98.62% and 98.56%, respectively. The proposed methodology performs more accurately in terms of prediction accuracy and age prediction deviation from the SOTA methodology.

The modern semiconductor electronic devices are becoming increasingly vulnerable to malicious implants called Hardware Trojans (HT). This problem is also greatly related to Printed Circuit Boards (PCB), which are widely used in almost all electronic devices. In this paper, two machine learning (ML) methods have been applied to detect HTs running on power from I/Os of legitimate chips on a PCB. A PCB prototype has been fabricated to obtain real-life data, which was used to train two ML algorithms: One-Class Support Vector Machine and Local Outlier Factor. For validation of the ML classifiers, one hundred categories of HT devices have been modelled and inserted into the Validation and Testing datasets. Simulation results show that using the proposed methodology an HT device can be detected with high prediction accuracy (F1-score above$99.7\%$for a$50mW$HT). Further, the ML model has been uploaded to the prototype PCB for hard-silicon validation of the methodology. To the best of our knowledge, this is the first work on real-time detection of PCB HTs, which are powered from the I/O pins of legitimate ICs. Experimental results show that the performance of the ML model on a real-life prototype is consistent with that of the simulations.

Integrated circuits (ICs) may be exposed to counterfeiting due to the involvement of untrusted parties in the semiconductor supply chain; this threatens the security and reliability of electronic systems. This paper focusses on the most common type of counterfeiting namely, recycled and remarked ICs. The goal is to develop a technique to differentiate between new and recycled ICs that have been used for a short period of time. Detecting recycled ICs using aging sensors have been researched using sub-threshold leakage current and frequency degradation utilizing ring oscillators (ROs). The resolution of these sensors requires further development to accurately detect short usage time. This paper proposes a differential aging sensor to detect recycled ICs using ring oscillators with sub-threshold leakage current to detect aging effects using bias temperature instability (BTI) and hot carrier injection (HCI) on a 22-nm CMOS technology, provided by GlobalFoundries. Simulation results confirm that we are able to detect recycled ICs with high confidence using proposed technique. It is shown that the discharge time increases by 14.72% only after 15 days and by 60.49% after 3 years' usage, and outperforms techniques that use frequency degradation only, whilst considering process and temperature variation.

Recycled ICs have become a major threat to the ICs used in safety critical systems. In the current state-of-the-art techniques, recycled ICs are detected by measuring the frequency, current, path delay or power-up values to estimate the HCI, BTI and EM effects on the transistors with age. Some of the state- of-the-art techniques require additional on-chip sensors to detect and estimate the age of an IC while others use existing logic like SRAM and Flip-flops to detect the recycled ICs. In this paper, we provide a methodology to detect a recycled IC and also to estimate its age by using the existing IO pad structures. For the first time, age is estimated by measuring voltage drop across the protection diodes present in IO pad structure. With this methodology, no additional sensors have to be added and hence there is no area overhead. With this proposed methodology, ICs that are used for a minimum period of a day can be effectively detected by using the concept of extended Kalman filtering technique for the first time in this domain. By stressing the part for five days, our proposed methodology can estimate the age of the IC aged between 1 month to 5 years with 95% percent of accuracy.

Electronic system components can fall prey to counterfeiting via untrustworthy parties in the semiconductor supply chain, which has established a worldwide span to reduce costs, time to market, and increase productivity. Recently, integrated circuits (ICs) counterfeiting has threatened systems security and reliability that utilize ICs in all domains. This article focuses on the most counterfeited area—recycled and remarked ICs—and aims to develop a technique to distinguish between new and used digital ICs based on an aging sensor mechanism. Aging sensors have been studied based on path-delay fingerprinting and ring oscillators (ROs) frequency degradation, but their resolution requires further development to accurately detect short usage. This study proposes a novel differential aging sensor to measure the discharge time ($\tau {{{dv}}}$) increase that depends on the subthreshold leakage current due to aging with two on-chip designs. Simulations were conducted using the GlobalFoundries (GF) 22 nm for aging with bias temperature instability and hot carrier injection (HCI) combined. The results show that the$\tau {{{dv}}}$increase is 14.72% after 15 days of usage and increases to 60.49% after three years. This further increases at higher temperatures; the highest simulated temperature ($125~^{\circ }\text{C}$)$\tau {{{dv}}}$increases by 55.93% after 15 days and 310.17% after three years. The proposed method also outperformed the traditional frequency degradation-based aging estimation method, which at nominal temperature is found to be 5.00% after 15 days and 23.68% after three years. Therefore, discharge time is a sensitive indicator for aging, surpasses frequency in detecting previous usage and is robust against process, voltage, and temperature variations (PVTs).

Aging is known to impact electronic systems affecting performance and reliability. However, it has been shown that it also brings benefits for power saving and area optimization. This paper presents highlights of those benefits and further shows how aging effects can be leveraged by novel methods to contribute towards improving hardware oriented security and reliability of electronic circuits. We have demonstrated static power reduction in complex circuits from IWLS05 benchmark suite, reaching a noticeable 7S% of reduction in ten years of operation. In hardware oriented security, a novel aging sensor has been proposed for detection of recycled ICs, measuring discharge time Tdv of the virtual power $(VV_{dd)}$ network in power-gated designs. This sensor utilizes discharge time of VVddnetwork through leakage current that is much more sensitive to aging than path delay, exhibiting up to 15.7X increment in 10 years. Furthermore, we show how frequency degradation caused by aging is used for online prediction of remaining useful lifetime (RUL) of electronic circuits. Results show an average RUL prediction deviation of less than 0.1 years. This methodology provides node calculations rather than a mean time to failure (MTTF) of the population. The set of techniques that are presented in this paper takes advantage of aging effects, having a positive impact in various aspects of microelectronic systems.

The CMOS aging, transient effects, and TSV thermomechanical stress degrade the resilience of 3D-ICs. The transients effects lead to soft errors and aggravated with the CMOS Bias temperature instability (BTI). In this paper, we analyze detrimental transient and BTI effect on soft error rate (SER) in 3D-ICs. However, TSV thermomechanical stress presents a considerable benefit by enhancing the critical charge (Qc) and reduce the SER due to decrease in the threshold voltage and increase in mobility of carriers in transistor present out of keep-out-zone and useful range. Therefore we propose a framework to evaluate the effect of transient, BTI, and TSV thermomechanical stress on critical charge and SER in 3D-ICs. Subsequently, through HSPICE simulation we show that for a lifetime of ten years and on the topmost layer of stacked 3D-IC, the reduction in SER of NAND gate by 5.12% - 9.05% and in 6T SRAM 2.51% - 4.76% and 3.77% - 5.64% decrease for storing 0 and 1 respectively.

In this paper, we propose a novel technique to detect recycled ICs via an on-chip, coarse-grained aging sensor, which can be applied to low-power circuits featuring power gating. The sensor detects the increase in the power-rail discharge time of power-gated circuits, when the circuit enters the sleep condition. Through HSPICE simulations, we prove that power network discharge time (τdV) is extremely sensitive to the age of the circuit. Indeed, after only 1 month of operation, τdVincreases by more than 3X and, after 1 year, its increase exceeds 7X. Our technique enables the detection of recycled ICs with a very high confidence and is a considerably more sensitive indicator of an aged device that alternative solutions relying on fine-grained performance degradation sensors.

Manufacturing defects that do not affect the functional operation of low power integrated circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesized using a 32 nm CMOS technology, the tradeoffs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of${R}~{\gtrsim }~{10~{ M}\Omega }$(weak bridges) and bridges of${R~\lesssim~10~{ M}\Omega }$(strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27 K and 157 K gate equivalents, respectively.

Regular and redundant through-silicon via (TSV) interconnects are used in fault tolerance techniques of 3-D IC. However, the fabrication process of TSVs results in defects that reduce the yield and reliability of TSVs. On the other hand, each TSV is associated with a significant amount of on-chip area overhead. Therefore, unlike the state-of-the-art fault tolerance architectures, here we propose the time division multiplexing access (TDMA)-based fault tolerance technique without using any redundant TSVs, which reduces the area overhead and enhances the yield. In the proposed technique, by means of TDMA, we reroute the signal through defect-free TSV. Subsequently, an architecture based on the proposed technique has been designed, evaluated, and validated on logic-on-logic 3-D IWLS'05 benchmark circuits using 130-nm technology node. The proposed technique is found to reduce the area overhead by 28.70%-40.60%, compared to the state-of-the-art architectures and results in a yield of 98.9%-99.8%.

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-power-network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3× and 1.45× the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.

TSV failures due to manufacturing defects and thermal-induced latent defects result in yield and reliability issues in 3D-ICs. Recent work has shown different temperature mitigation techniques and fault tolerant architectures for 3D-ICs. It is known that TSVs are effective in reducing temperature by providing thermal conductivity. This is the first work that jointly considers temperature mitigation and fault tolerance for TSV based 3D ICs without introducing additional redundant TSVs (also called dummy TSVs). By reusing and carefully placing spare TSVs that are frequently deployed for improving yield and reliability in 3D ICs, temperature is reduced without affecting fault tolerance capability. The proposed technique consists of two steps: first is TSV determination step, which provides optimised allocation of regular and spare TSVs in groups to achieve expected repair capability. The second step is TSV placement, where, for the first time, temperature mitigation is addressed when considering TSVs impact on both vertical and horizontal heat flow. Meanwhile routing difference and total wirelength can be co-optimized. Simulation results show that using the proposed technique, 100% repair capability is achieved across all (five) benchmarks with an average temperature reduction of 33% (best case is 58.2%), while the wirelength may slightly increase depending on assumed TSV fault rate.

In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for power-gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32-nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test chip manufactured with a 65-nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower$V_{\textrm {th}}$compared with the standard STs. This can be achieved by either redesigning the STs with the identified$V_{\textrm {th}}$value or applying a proper forward body bias to the available power switching fabrics. Through the HSPICE simulations, we show LT extension up to$21.4\times $and average static power reduction up to 16.3% compared with the standard ST design approach, without additional area overhead. Finally, we show LT extension and several performance-cost tradeoffs when a target maximum LT is considered.

In this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead. Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4%.

This paper examines diagnosis of power switches when the power-distribution-network (PDN) is considered as a high resolution distributed electrical model. The analysis shows that for a diagnosis method to perform high diagnosis accuracy and resolution, the distributed nature of PDN should not be simplified by a lumped model. For this reason, a PDN-aware diagnosis method for power switches fault grading is proposed. The proposed method utilizes a novel signature generation design-for-testability (DFT) unit, the signatures of which are processed by a novel diagnosis algorithm that grades the magnitude of faults. Through simulations of physical layout SPICE models, we explore the trade-offs of the proposed method between diagnosis accuracy and diagnosis resolution against area overhead and we show that 100% diagnosis accuracy and up to 98% diagnosis resolution can be achieved with negligible cost.

We propose a novel dynamic voltage scaling (DVS) approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose a BTI and leakage aware selection of the “drowsy” state retention voltage for DVS of cache memories. We propose three DVS policies, allowing us to achieve different power/reliability trade-offs. Through SPICE simulations, we show that a critical charge and a static noise margin increase up to 150% and 34.7%, respectively, is achieved compared to standard aging unaware drowsy technique, with a limited leakage power increase during the very early lifetime, and with leakage energy saving up to 37% in 10 years of operation. These improvements are attained at zero or negligible area cost.

In this paper, we show that the vulnerability of memory components due to data retention in the presence of soft errors exhibit orders of magnitude variations with applications through extensive analysis of MiBench benchmarks. Underpinning such analysis, we propose a novel application-specific design flow for joint energy efficiency and reliability optimization. The energy efficiency is achieved through voltage/frequency scaling (VFS), while reliability is achieved through suitably choosing the appropriate protection policies (L1-Cache resizing and selective ECC) for hierarchical memory components. Fundamental to such joint optimization is a design analysis framework, which can analyze trade-off between memory protection policies considering the impact of VFS, and apply design optimization algorithm to provide with an energy-efficient design, while meeting a given reliability target. Using this framework the proposed design flow is validated through extensive number of application case studies based on ARMv7 processors modeled in GEM5. We show that the joint consideration of cache resizing and VFS can improve the L1-Cache reliability by up to 5x compared to VFS alone, while incurring <10% energy overhead. Additionally, using selective ECC for L2-Cache and DRAM, we show that energy consumption can be reduced by up to 40%.

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles.

This brief presents the design, validation, and evaluation of an efficient online fault tolerance technique for fault detection and recovery in presence of three through-silicon-vias (TSV) defects: 1) voids; 2) delamination between TSV and landing pad; and 3) TSV short-to-substrate. The technique employs transition delay test for TSV fault detection. Fault recovery is achieved by employing redundant TSVs and rerouting signals to fault-free TSVs. This technique is efficient because it requires a small (2× number of TSVs per group) number of clock cycles for fault detection and recovery. Synthesis results using 130-nm design library show that 100% repair capability can be achieved with low area overhead (4% for the best case).

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality.

SPICE offers an accurate method of simulating defect behavior. However, as demonstrated by recent research, it requires long computation time to simulate defect behavior, when considering process variation. To the best of our knowledge, there is no efficient variation-aware delay fault simulation methodology for resistive opens and resistive bridges. This paper presents a fast and accurate delay fault simulation methodology for these two defects. It is fast because it speeds up delay fault computation time by employing two efficient algorithms. The first algorithm is used to calculate transient gate output voltage, which is a key variable needed to compute delay faults. It employs a three step strategy to accelerate the computation of transient gate output voltage without compromising accuracy. The second algorithm uses bisection method to efficiently compute delay fault behavior of a fault-site. The proposed methodology (PM) has been incorporated in an open-source SPICE (NGSPICE) with BSIM4.7 transistor model. The methodology has been validated by comparing results with HSPICE using industrial designs from IWLS 2005 benchmarks and realistic fault-sites have been extracted from synthesized designs. Simulations are carried out using a 65-nm gate library (for illustration). When compared with HSPICE, results show that the PM is on average up to 52-times faster with ≤ 4.2% error in accuracy for resistive open and 39-times faster with ≤ 5.2% error in accuracy for resistive bridge defects.

Power switches are used as a part of the power-gating technique to reduce the leakage power of a design. To the best of our knowledge, this is the first report in open literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes the recently proposed design-for-test solution for efficient testing of power switches in the presence of process, voltage, and temperature variation. It divides power switches into segments such that any faulty power switch is detectable, thereby achieving high diagnosis accuracy. The proposed diagnosis method is validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that, when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; it is less than 12% when considering VT variations.

Three-dimensional Integrated Circuits (3D-ICs) vertically stack multiple silicon dies to reduce overall wire length, power consumption, and allow integration of heterogeneous technologies. Through-silicon-vias (TSVs) which act as vertical links between layers pose challenges for 3D integration design. TSV defects can happen in fabrication process and bonding stage, which can reduce the yield and increase the cost. Recent work proposed the employment of redundant TSVs to improve the yield of 3D-ICs. This paper presents a redundant TSVs grouping technique, which partitions regular and redundant TSVs into groups. For each group, a set of multiplexers are used to select good signal paths away from defective TSVs. We investigate the impact of grouping ratio (regular-to-redundant TSVs in one group) on trade-off between yield and hardware overhead. We also show probabilistic models for yield analysis under the influence of independent and clustering defect distributions. Simulation results show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratios lead to achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. Using transition delay test, this paper analyzes the behavior of resistive bridge defect under the influence of process variation. The effect of process variation is incorporated by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (μeff), where each follows Gaussian distribution. Through HSPICE simulations using a 65-nm gate library, this paper brings the following two contributions: firstly, it analyzes the delay behavior of bridge defect using all three transition delay classes to determine the most effective class of transition test that achieves maximum coverage in the presence of process variation. Secondly, recent research has shown that low voltage testing improves detectability of bridge fault, this work compares bridge resistance coverage using logic test and delay test at multiple voltage settings to identify the best voltage setting and test type for detecting resistive bridge defects.

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.

State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software, respectively. To validate the methodology, ARM® Cortex™-M0 embedded microprocessor (provided by our industrial project partner) is implemented in field-programmable gate array and further synthesized using 65-nm technology to quantify the cost in terms of area, latency, and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multibit errors for a wide range of fault rates.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present, there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using the BSIM4 transistor model. To speed up the computation time and without compromising simulation accuracy (achieved through BSIM4), two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65 nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE.

Power gating is an effective technique for reducing leakage power which involves powering off idle circuits through power switches, but those power-gated circuits which need to retain their states store their data in state retention registers. When power-gated circuits are switched from sleep to active mode, sudden rush of current has the potential of corrupting the stored data in the state retention registers which could be a reliability problem. This paper presents a methodology for improving the reliability of power-gated designs by protecting the integrity of state retention registers through state monitoring and correction. This is achieved by scan chain data encoding and decoding. The methodology is compatible with EDA tools design and power gating control flows. A detailed analysis of the proposed methodology's capability in detecting and correcting errors is given including the area overhead and energy consumption of the protection circuitry. The methodology is validate using FPGA and show that it is possible to correct all single errors with Hamming code and detect all multiple errors with CRC-16 code. To the best of our knowledge this is the first study in the area of reliable power gating designs through state monitoring and correction.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (μeff), where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE.

The use of multiple voltage settings for dynamic power management is an effective design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% fault coverage; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective gate sizing technique for reducing test cost of multi-Vdddesigns with bridge defects. Using synthesized ISCAS and ITC benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves singleVddtest, without affecting the fault coverage of the original test. In addition, the proposed technique performs better in terms of timing, area, and power than the recently proposed test point insertion technique. This is the first reported work that achieves singleVddtest for resistive bridge defects, without compromising fault coverage in multi-Vdddesigns.

Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lower overhead than the recently proposed test point insertion technique in terms of timing, area and power.

This paper analyzes the behavior of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesized International Symposium on Circuits and Systems benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation.

Multiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost.

Multiple-voltage is an effective dynamic power reduction design technique, commonly used in low power ICs. To the best of our knowledge there is no reported work for diagnosing multiple-Vdd enabled ICs and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. Using synthesized ISCAS benchmarks, with realistic extracted bridges and parametric fault model; the paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multi-Vdd diagnosis algorithm.

A key design constraint of circuits used in hand-held devices is the power consumption, mainly due to battery-life limitations. Adaptive power management (APM) techniques aim at increasing the battery life of such devices by adjusting the supply voltage and operating frequency, and thus the power consumption, according to the workload. Testing for resistive bridging defects in APM-enabled designs raises a number of challenges due to their complex analog behavior. Testing at more than one supply voltage setting can be employed to improve defect coverage in such systems; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes a multi- automatic test generation method which delivers 100% resistive bridging defect coverage and also a way of reducing the number of supply voltage settings required during test through test point insertion. The proposed techniques have been experimentally validated using a number of benchmark circuits.

A key design constraint of circuits used in handheld devices is the power consumption, due mainly to the limitations of battery life. The employment of adaptive power management (APM) methods optimizes the power consumption of such circuits. This paper describes an effective APM-aware DFT technique that consists of a Test Generation Suite, including fault list generation, test pattern generation and fault simulation. The test generation suite is capable of generating test patterns for multiple supply voltage (Vdd) settings to maximize coverage of resistive bridging faults; and a method to reduce the number of Vdd settings without compromising the fault coverage in order to reduce the cost of test. Preliminarily validations of the proposed DFT technique using a number of benchmark circuits demonstrate its effectiveness.

The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors' technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using a state traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques

In this paper we present efficient Reverse Order Restoration (ROR) based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation based restoration of test subsequences, our technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using State Traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques.