Static learning has been used to improve structural Automatic Test Pattern Generation (ATPG) results by reducing backtracks and thus aborted faults. However, static learning is limited to simple relationships and can generate massive learning data, most of which is not needed during ATPG. We present a new dynamic learning technique to learn only needed relationships that can include multiple gates and time frames. We show improved coverage and pattern count on industrial design.

Static learning, performed before Automatic Test Pattern Generation (ATPG), guides ATPG decisions and can improve ATPG results, i.e., coverage and pattern count. We present new techniques to efficiently perform static learning on large industrial designs using both structural ATPG as well as a Satisfiability solver (SAT). The number of learned ties and equivalences can reach many millions, even after pruning "non-worthwhile" relationships. To the best of our knowledge, this is the first work to show effective static learning results on industrial designs.

Logic Built-In Self-Test (LBIST) is becoming a requirement for high-complexity, high-reliability ICs which are increasingly used in the automotive field. Traditionally, LBIST can only be applied when there are no unknown simulation values (Xs) which would render the LBIST signature unusable. Eliminating all Xs in large industrial designs, especially when containing third party hard IP blocks, can be difficult, and anticipating all possible X-sources can be impractical. We present an X-tolerant LBIST solution (XLBIST) which uses compressor/decompressor structures, including X-control logic, that have already been inserted in the design for scan-compression deterministic patterns. Automatic test pattern generation (ATPG) leverages these structures to generate efficient XLBIST patterns. Patterns can be generated for any number (or density) of Xs, with resulting test coverage tradeoff. Results on industrial designs with high X densities demonstrate consistent XLBIST coverage.

For more than two decades, the key objective for synthesis of linear decompressors has been maximizing encoding efficiency. For combinational decompressors, encoding satisfiability is dynamically checked for each specified care bit. By contrast, for sequential linear decompressors (e.g. PRPGs), encoding is performed for each test cube; the resultant static encoding considers that a test cube is encodable only if all of its care bits are encodable. The paper introduces a new class of sequential linear decompressors that provides a trade-off between the computational complexity and the encoding efficiency of linear encoding. As a result, it becomes feasible to dynamically encode care bits before a test cube has been completed, and derive decompressor-implied scan cell values during test generation. The resultant dynamic encoding enables an identification of encoding conflicts during branch-and-bound search and a reduction of search space for dynamic compaction. Experimental results demonstrate that dynamic encoding consistently outperforms static encoding in a wide range of compression ratios.

High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.

As scan compression becomes ubiquitous, ever more complex designs require higher compression. This paper presents a novel, two-level compression system for scan input data generated by deterministic test generation. First, load care bits and X-control input data are encoded into PRPG seeds; next, seeds are selectively shared for further compression. The latter exploits the hierarchical nature of large designs with tens or hundreds of PRPGs. The system comprises a new architecture, which includes a simple instruction-decode unit, and new algorithms embedded into ATPG. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage and performance.

Scan testing and scan compression have become key components for reducing test cost. We present a novel technique to increase automatic test pattern generation (ATPG) effectiveness by identifying and exploiting instances of increasingly common “majority gates”. Test generation is modified so that better decision are made and care bits can be reduced. Consequently, test coverage, pattern count and CPU time can be improved. The new method requires no hardware support, and can be applied to any ATPG system, although scan compression methods can benefit the most.

Scan testing and scan compression are widely used, but ever more complex designs require higher compression, while the increased density of unknown (X) values reduces effective compression. In this paper, we present a new selector design which blocks all Xs while allowing more observability of non-X scan cells and which requires fewer input control values. Supported by novel test generation algorithms, the selector enables very high compression even if the density of unknown values is very high and varies every shift. Results on industrial designs with various X densities demonstrate consistently high compression and test coverage.

Full scan designs are widely used for their indisputable benefits of predictably high test coverage, diagnosis and debug. However, for high-performance designs the cost of scan - area and delay - is not acceptable and partial scan is used instead. Unfortunately, partial scan significantly increases test generation complexity. We define a structured partial scan design methodology and specific test generation enhancements, which significantly enhance test coverage and reduce test data and cycles. Selective design areas use special types of nonscan cells which can capture a value in the last few scan load cycles. Combinational test generation is extended to work with this structured partial scan design, resulting in higher coverage and fewer patterns. Experimental results on industrial designs show consistent testability benefits.

This paper presents a new X-blocking system which allows very high compression and full coverage even if the density of unknown values is very high and varies every shift. Despite the presence of Xs in scan cells, compression can be maximized by using PRPG and MISR structures. Results on industrial designs with various X densities demonstrate consistently high compression and full test coverage.

To leverage the computing power of multicore machines in ATPG, we developed a highly efficient parallel ATPG system based on dynamic fault partition and shared memory. The system takes advantage of built-in efficiency of parallel search to achieve good performance speedup with no sacrifices in pattern quality or test coverage.

Scan testing and scan compression have become key components for reducing test cost, and most high-compression schemes are based on linear, sequential compressors e.g., pseudo-random pattern generators (PRPG). We present a novel technique to increase PRPG-based compression by modifying test generation so that justification of certain decision nodes is delayed and merged with PRPG seed computation. Our method does not affect test coverage or diagnosis, requires no hardware support, and can be applied to any linear compression scheme. Results on industrial designs demonstrate consistent increase in compression.

Scan testing and scan compression are key to realizing cost reduction and quality control of ever more complex designs. However, compression can be limited if the density of unknown (X) values is high. We present a method to identify a small, but important, subset of scan cells that are "likely" to capture an X, place them on separate "X-chains", create a combinational unload compressor tuned for these X-chains, and modify test generation to take advantage of this circuit. This method is fully integrated in the design-for-test (DFT) flow, requires no additional user input and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.

Traditional scan and, more recently, scan compression are increasingly accepted for reducing test cost and improving quality in ever more complex designs. Combinational scan compression techniques are attractive for their low impact on area, timing and design flow, but are best suited for designs with a limited number of unknowns (Xs). However, recent design performance and cost tradeoffs create a much higher density of Xs than previously expected. We present a combinational scan compression method that preserves the low-impact advantages, while also allowing any number and distribution of Xs with virtually no loss of test quality. Results on industrial designs with a varied density of Xs demonstrate consistent data and test time compressions with negligible impact on all design parameters.

Scan is widely accepted as the basis for reducing test cost and improving quality, however its effectiveness is compromised by increasingly complex designs and fault models that can result in high scan data volume and application time. The authors present a scan compression method designed for minimal impact in all aspects: area overhead, timing, and design flow. Easily adopted on top of existing scan designs, the method is fully integrated in the scan synthesis and test generation flows. Data and test time compressions of over 10times were obtained on industrial designs with negligible overhead and no impact on schedule.

Tristate buses, commonly used in high-performance designs, raise testability problems because one-hot conditions, required for functional operation, may not be maintained during scan testing. We present a novel method to automatically generate and insert a bus encoder that ensures one-hot bus operation. Each bus is analyzed individually; a customized encoder is then generated and optimized for best testability and minimal area and delay. We introduce two new bus encoder designs which form the basis of a hierarchically algorithm that scales up to any number of bus inputs.

Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression

Scan-based tests created by automatic test pattern generators (ATPG) can be efficiently compressed and applied in a deterministic built-in self-test (DBIST) architecture. However, the BIST environment adds significant complexity to failure diagnosis. We present a simple scan-compatible diagnosis solution - streaming DBIST (SDBIST), which is based on a low-overhead hierarchical compactor SDBIST allows continuously monitoring streaming scanout data for reduced-volume expect-data diagnosis, on-line fail-data collection and selective scan cell masking.

X-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. In this paper we introduce a novel selector architecture that allows arbitrary compression ratios, scales to any number of scan chains and minimizes area overhead. XDBIST test-coverage, full X-tolerance and scan-based diagnosis ability are preserved and are the same as deterministic scan-ATPG.

We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern generator (ATPG) and are encoded as linear feedback shift register (LFSR) initial values (seeds); one or more patterns can be encoded into a single LFSR seed. During test application, seeds are loaded into the LFSR with no cycle overhead. The method presented achieves reductions of at least 100x in test data and 10x in tester cycles compared to deterministic ATPG while maintaining complete fault coverage, as confirmed by experimental results on industrial designs.

Logic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern generation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper proposes an interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hardware overhead. Tester fail-data collection is based on a novel construct incorporated into the design-extensions of the standard test-interface language (STIL). The implementation of the proposed method is presented and analyzed.

As a result of increasing design size and complexity, the multiple clock domain design style has become a new trend in the industry. Several techniques to test circuits with multiple clocks are known; however, they often result in increased test time and tester memory for large and complex circuits. This paper presents a strategy to reduce the test pattern count during ATPG by forcing a safe capture behavior when multiple clocks are applied during capture. The usage of multiple clocks allows additional observability, which can significantly reduce the pattern count for circuits with many clocks. Experimental results indicate that proposed strategy results in larger and moreover, more consistent reduction in test sizes.

Originally developed decades ago, logic built-in self-test (BIST) evolved and is now increasingly being adopted to cope with rapid growth in design size and complexity. Compared to deterministic pattern test, logic BIST requires many more test patterns, and therefore, increased test time unless many more internal scan chains can be shifted in parallel. To match this large number of scan chains, the width of the signature analyzer would have to be enlarged, which would result in large area overhead and signature storage space. Instead, a combinational space-compactor is inserted between the scan chain outputs and the signature analyzer inputs. However, the compactor may deteriorate the ability to test and diagnose the design. This paper analyzes how compactors affect test and diagnosis and shows that compactors can be designed to actually improve the testability of certain faults, while providing full diagnosis capability. Algorithms that allow automated design of optimal compactors are presented and results are discussed.

Design and test tools, such as automatic test-pattern generators (ATPG) and fault-simulators, work on a "flattened" simulation model of the entire design. Run-time performance is directly influenced by the number and complexity of simulation primitives in the flattened model. Moreover, the memory required to flatten and store the simulation model of current multi-million-gate designs may exceed the available address space of 32 bit computers. We present several model-optimization techniques that significantly reduce the number of simulation primitives and the associated memory usage while still preserving a complete, highly efficient flattened model. A commercial ATPG product implementing these techniques demonstrates fast simulation model construction for very large designs using a relatively small memory space.

Significant engineering effort is invested into coding libraries for automatic test pattern generation (ATPG) and verifying their equivalence with corresponding "golden" simulation libraries. These tasks are greatly simplified by using the methodology and the ATPG described in this paper. Simulation libraries are read-in with little or no recoding. Various structural and some behavioral Verilog constructs are automatically converted into efficient gate-level models for ATPG.

Most library development effort is invested in coding and verifying custom or special function cells that cannot be easily represented by traditional gates such as AND, OR, and are naturally encoded as tables. The library reader described in this paper reads in existing simulation libraries and converts tables into efficient gate-level models for use by test-generation and other tools, thus automating the most engineering-intensive task of library development.

Developed for pattern interchange from test-generation output to tester input, the standard test interface language (STIL) was recently shown to support general test-generation input constructs. This paper shows how scan-test rules-checking can be driven by a single STIL input file. All rules-checking information can be read back in to iteratively refine rules checking.

The Standard Test Interface Language (STIL) was developed for universal pattern interchange form test generation tools output to tester input. We extend the usage of STIL to the various input files of a test generation tool we developed, thus using one language where traditional test tools use five or more. This significantly reduces engineering time to learn the required languages, create and maintain all files. The output STIL file generated contains the information from ail input files, eliminating the confusion often caused by managing multiple versions of multiple files. Users can start with only a minimal input file, have the tool fill in defaults, and write out a complete STIL file. This file can be modified and read back in as any of the input files, allowing stepwise refinements.

Structured Design-For-Testability (DFT) employs automated Design-Rules-Checking (DRC) to ensure a design is testable and test patterns can be produced using Automated Test Pattern Generation (ATPG). Central to DRC are ATPG-related clock rules. This paper defines a robust set of clock rules and their implementation for scan designs. It then extends clock-rule-violation detection beyond test requirements, which provides fast clock verification early in the design cycle, complementing the more complex and slower timing tools. Results on a large microprocessor design show the applicability of ATPG-based timing verification.

Scan test patterns are typically generated by ATPG tools which use a zero delay simulation model. These scan test patterns have to be verified using a golden simulator which is approved by the chip foundry with full timing before the patterns are accepted for manufacturing test. This can be very time consuming for many designs because of the size of the test data and the large number of test cycles which have to be simulated. A universal technique for accelerating scan test pattern simulation which can be used for any simulator with any scan cell type from any foundry is proposed. The extensions to test data languages to support universal acceleration of scan pattern simulation are also proposed. Some experiment results are also provided.

When creating scan-based ATPG patterns: it is often necessary to constrain those patterns to satisfy certain conditions such as avoiding bus contention. A method is described that supports defining general pattern restrictions that are partitioned to allow efficient test generation.

This paper presents a new effective scheme to decompress in parallel deterministic test patterns for circuits with multiple scan chains. Two implementations of the scheme are discussed. In the first one, the patterns are generated by the reseeding of a hardware structure which is mostly comprised of the already existing DFT environment. In the second approach, the patterns are generated through the execution of a program on a simple embedded processor. Extensive experiments with the largest ISCAS'89 benchmarks show that the proposed technique greatly reduces the amount of test data with low cost. Efficient automatic test pattern generation algorithms are also presented to enhance the efficiency of the proposed approach.

High-performance, complex CMOS designs such as microprocessors continue to gain performance by the use of "non-conventional" circuits such as tri-state, ratio or precharged logic. Such circuits are also used in noncomplementary or DC-redundant structures. While such design styles are not really new, their widespread use in very large, complex circuits (e.g., microprocessors) make "conventional" fault modeling and test generation ineffective. This paper describes test generation techniques to handle such circuits without affecting their performance or area. These techniques exploit circuit particularities of noncomplementary CMOS design in fault modeling, use automatic learning of useful relations about nodes in the design, and innovative test vector generation. On several designs ranging up to 2.5 million gates, the combined application of these methods increased test coverage from 50% to 100% while decreasing CPU time by orders of magnitude.

A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described. This system is formed by optimally combining a fast fault simulator with a powerful test generator. For the ISCAS85 and ISCAS89 circuits, this ATPG system created a test for all testable faults and identified all redundant faults without a single aborted fault. This represents the first time this has been achieved for the ISCAS89 designs, and the performance of this ATPG system is significantly better than published results. Performing ATPG for the largest ISCAS89 designs, which contained about 25000 gates, required only 3 min of CPU time on an Apollo DN3550 workstation. The data collected for the ISCAS designs showed that the ATPG CPU time increased linearly with gate count. This strongly suggests that ATPG can be efficiently performed for circuits of 100000 and even one million gates.>

Defects in integrated circuits can cause delay faults of various sizes. Testing for delay faults has the goal of detecting a large fraction of these faults for a wide range of fault sizes. Hence, an evaluation scheme for a delay fault test must not only compute whether or not a delay fault was detected, but also calculate the sizes of detected delay faults. Delay faults have the counterintuitive property that a test for a fault of one size need not be a test for a similar fault of a larger size. This makes it difficult to answer questions about the sizes of delay faults detected by a set of tests. A model for delay faults that answers such questions correctly, but with calculations simple enough to be done for large circuits, is presented.>

Motivated by the advances in fast fault-simulation techniques for large combinational circuits, a panel discussion was organized for the 1988 International Test Conference. A collective account of the position statements is offered by the panelists. The panelists present discussions on the following topics: introduction to fault simulation; parallel pattern fault simulation; intelligent heuristics; graph-theoretic approaches; approximate solutions; hierarchical fault simulation; and hardware solutions.>

Performance results are given for use of a weighted random pattern test generator, WRP, on ten benchmark designs. Deterministic (DET) and WRP tests created for single stuck faults are compared in their ability to detect shorts and transition faults. The WRP is able to generate a test for all the single stuck faults detected with a state-of-the-art deterministic pattern generator; WRP is highly efficient in CPU time required for full stuck fault test pattern generation; both DET and WRP achieved high net-to-net shorts fault coverage on a sample of ten designs; and WRP had significantly higher ( approximately=11%) transition fault coverage than obtained with DET for the same sample.>