In this paper a novel ring oscillator based VCO using a programmable low-dropout regulator (LDO) for coarse frequency tuning, which offers wide tuning range, low phase noise and low die area for integer or fractional-N PLLs is proposed. This design is using two paths to cover more frequencies. The high frequency path uses three delay cells, while the lower frequency path enables two more delay cells to reduce the output frequency. The frequency coverage is 2.75 – 3.7 GHz and 4.5 – 5.7 GHz. Finally, the ring oscillator is designed using 65nm TSMC process with a supply voltage of 1.5V for the LDO and 1 - 1.4V for the ring oscillator. The phase noise is -99.78 dBc/Hz at 1MHz offset, while the power consumption of the full design is 29mW.

On-chip monitor (OCM) circuits capture dynamic power-supply (PS) waveforms within power domains individually bounded by dedicated micro voltage regulator modules (μVRMs). This paper uses OCM to diagnose VLSI circuits with a modular power management, where the evolution over time of the gate switching count, in the clock tree, the flip-flops, and the combinational logics are precisely captured in the OCM voltage waveforms. A mismatch between simulation and measurement gives us a warning for either (1) faulty behavior in the IC hardware, or (2) bugs in the test program. In this paper, we demonstrate an IR-drop-based toggle diagnosis technique using OCM for a prototype chip in 180 nm technology. The OCM measurements at 100 ps and 100 μV are capable of reaching a resolution of 18.7 fC/gate. This is approximately equivalent to the amount of charge consumed by a single two-input NAND gate.

Mixed-signal applications constitute a significant trend in the semiconductor industry. Huge effort is focused on creating fast and accurate mixed-signal designs, which include both analog and digital parts. A widely used mixed-signal circuit in modern electronics is the Sigma-Delta analog-to-digital converter (ADC). Sigma-Delta modulation is mainly exploited as a method for encoding analog signals into digital signals as found in an ADC. Apart from that, it is used to convert high bit-count, low-frequency digital signals into lower bit-count, higherfrequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC). In this work, a first-order Sigma-Delta ADC real number model using SystemVerilog is presented, in order to greatly improve simulation efficiency while keeping accuracy in a satisfying level. The proposed sigma-delta ADC real number model consists of a sigma-delta modulator, a digital filter and a decimator. The design and simulation of the proposed Sigma-Delta ADC model was accomplished using the Cadence Incisive Enterprise Simulator. Moreover, the proposed model is compared to a Verilog-AMS Sigma-Delta ADC, having its design implemented and simulated in Cadence Virtuoso and Spectre AMS Designer. In all test cases, the presented SystemVerilog-based real number model displays high simulation time gains, along with acceptable accuracy.

In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. State-of-the-art ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional level. Two-dimensional System-on-Chips (2D-SoCs) and three-dimensional stacked ICs (3D-SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are tested ('module-under-test', MUT). In this work, we present the impact of the switching activity in the currently not-tested modules (which we refer to as 'neighbors' of the MUT) on overall IR-drop and propose a method to provide realistic conditions during modular test of digital 2D-SoCs and 3D-SICs, using on-chip programmable toggle generators.

A study on the coupling through substrate using the case of two square metal pads over bulk silicon substrate with epitaxial layer is presented. A lightly doped profile is adopted and it is simulated by means of an electromagnetic simulator for various pad distances and different metal layers, assuming a 65 nm bulk CMOS technology. Suggestions how to reduce the simulation time when a large number of isolation layers is involved are also provided. Furthermore, the increase of isolation (resulting in reduction of the noise coupling) between the pads by using proper metal guard rings is also analyzed and the impact of various guard ring design (geometrical) parameters is examined. S parameters are used to compare the various structures. A substrate circuit-model is proposed and evaluated for frequencies above 30 GHz.

The case of a defected TSV that has been cracked at the point where an impurity or a void hole originally had been is analyzed in this study. A lumped analytical electrical circuit that models the behavior of this defect is proposed. TSV fault modeling offers assistance in developing new test methods that would improve the reliability of the 3D ICs. The structure is simulated using a commercial 3D resistance, capacitance and inductance extraction tool. A test method that determines the possible characteristics of the defect is presented.

A lumped analytical electrical model for cracked (open fault) TSVs is proposed in this paper. Accurate and reliable fault models can support the test methods for the possible defects and they can be vital to improve the quality of TSV-based 3D-ICs. The model is verified by simulations using a commercial 3D resistance, capacitance and inductance extraction tool. The presented simulation results are in close agreement with the proposed analytical expressions.

In this paper the comparison of input stimulus signals using an adaptive FPGA-based testing system based on a method utilising wavelet transformation of the current waveforms is presented. The testing scheme is innovative because it offers the ability of applying different input stimulus signals with respect to the requirements of the examined circuit. Moreover, the method used is simple, offers a single-point test measurement solution and may easily be adapted to test various other analog and mixed-signal systems. Experimental results are presented showing the effectiveness of the proposed testing scheme.

A new source follower type analog buffer used as an output buffer for the data / column driver of an Active Matrix display is presented in this paper. The proposed buffer is implemented with low temperature polycrystalline silicon thin film transistor (LT poly-Si TFTs) and the main advantage of the buffer is its high immunity to the threshold voltage variation of the LT poly-Si TFTs. The functionality of the buffer is verified through simulation with HSpice, using for the simulations parameters extracted from fabricated LT poly-Si TFTs in order to obtain realistic simulation results.

A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.

A method for computing mutual inductance between interconnects of rectangular geometry in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is general and does not rely on any fitting techniques. It is shown to be computational efficient and numerical stable even for very long interconnects. Simulation results with other methods from literature are presented. The mutual inductance value computed by the proposed method is shown to be in close agreement to the value obtained by the industry standard tool-FastHenry with the average error falling below 5%.

Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come. Through-silicon-vias (TSV) processes offer a step towards 3D integration. In this work, the aspects of inductors in the TSV technologies are studied. Various TSV inductor topologies are examined both theoretically and by means of numerical simulations. As results show, true 3D vertical inductor designs offer improvements in inductance and quality factor over the planar ones.

In this paper a test method based on the wavelet transformation of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform, is presented. In the wavelet analysis, a test metric named discrimination factor is introduced utilizing information from initial two decomposition levels of the measured signal. The tolerance limit for the good circuit is set by statistical processing data obtained from the fault-free circuit. Experimental comparative results between the proposed method, a test method based on the RMS value of the measured signal, a test method utilizing the harmonic magnitude components of the measured signal spectrum and a method based on the wavelet transformation of the measured signal are presented showing the effectiveness of the proposed testing scheme.

In this paper a test method based on the wavelet transformation of the measured supply current (IPS) and load current (IL) waveforms is presented. In the wavelet analysis, the test metrics used are utilizing the initial three decomposition levels of the measured signal. Experimental comparative results between the proposed method, a test method based on the RMS value of IPS, a test method utilizing the harmonic magnitude components of the IPSspectrum and a method based on the wavelet transformation of the IPSare presented showing the effectiveness of the proposed testing scheme.

A comparison is made between model parameter calculation equations of RF CMOS inductors. Model parameters can be extracted from different equations using as variables either Y-, Z-parameters depending on the circuit configuration of the inductor or S-parameters. Results are based on on-wafer RF S-parameter measurements of a fabricated inductor. Differences appear between results obtained with calculation equations based on Z- and S-parameters, extracted for a differentially driven inductor. Therefore, care must be taken by the designers when evaluating an integrated inductor performance to comprehend the technological and operating environment of the device and to choose the corresponding formulas accordingly.

This work analyzes different parameter extraction methods for on-chip integrated inductors and assesses and their impact on inductor design. The relationship between extracted single-ended and differential parameters is investigated through the use of theoretical network models that support the calculation equations. Experimental results from a test chip are presented and a lumped model, which adequately simulates the inductor performance with and without ground shield, is validated in comparison to the simple nine-element model

The influence of the light illumination on the drain current of polycrystalline silicon thin-film transistors is studied in this work. The increase of the output current as a result of raised light intensity is modeled, based on measured experimental data for different Vdsand Vgsvalues. The proposed model has been verified against the measurements and the simulated output characteristics give a good approximation in the sub-threshold region

Polysilicon thin-film technology has become of great interest due to the demand for large area electronic devices. Display applications, memories and optical copier are among the fields where polysilicon thin-film transistors (poly-Si TFTs) are most commonly used. However the design of analogue blocks, by using Poly-Si TFTs, with constant specifications is very difficult because of the large variation of the threshold voltage of the poly-Si TFT across the wafer and the kink effect makes. In this paper we propose a circuit that can sense the voltage difference between two TFTs. This voltage can be used in order to design an improved current mirror with cancellation of threshold voltage variation

Fault detection in linear bipolar integrated circuits using power supply current measurements is investigated. The most prevalent, catastrophic and parametric faults, have been modelled for the representative (741 type) op amp. The circuit is simulated in both linear and non-linear operations. Comparative results between power supply current and output voltage measurements are given, showing the improvement in fault coverage by the use of the current sensing method.>

The system is designed for data-acquisition and computation of a relatively large number of parameters of a single twitch or tetanic contraction generated by an electrically stimulated skeletal muscle. The parameters that can be computed using the program facilities are: (i) the rise time (Tc), 50% relaxation time (50% Tr) and the maximum tension (Pt) of the twitch contraction; (ii) the approximate number of motor units innervating the muscle and the fatigue index; (iii) the fusion frequency of the tetanic contraction and the twitch to tetanus ratio; (iv) the maximum tetanic tension (P0) and its Tc and 50% Tr; (v) the P0 versus muscle length diagram; (vi) the fatigue-time course.