Time lag and quantization in temperature sensors in enterprise servers lead to stability concerns on existing variable fan speed control schemes. Stability challenges become further aggravated when multiple local controllers are running together with the fan control scheme. In this paper, we present a global control scheme which tackles the concerns on the stability of enterprise servers while reducing the performance degradation caused by the variable fan speed control scheme. We first present a stable fan speed control scheme based on the ProportionalIntegral-Derivative (PID) controller by adaptively adjusting the PID parameters according to the operating fan speed and eliminating the fan speed oscillation caused by temperature quantization. Then, we present a global control scheme which coordinates control actions among multiple local controllers. In addition, it guarantees the server stability while minimizing the overall performance degradation. We validated the proposed control scheme using a presently shipping commercial enterprise server. Our experimental results show that the proposed fan control scheme is stable under the non-ideal temperature measurement system (10 sec in time lag and 1°C in quantization figures). Furthermore, the global control scheme enables to run multiple local controllers in a stable manner while reducing the performance degradation up to 19.2% compared to conventional coordination schemes with 19.1% savings in power consumption.

Server consolidation plays a key role to mitigate the continuous power increase of datacenters. The recent advent of scale-out applications (e.g., web search, MapReduce, etc.) necessitate the revisit of existing server consolidation solutions due to distinctively different characteristics compared to traditional high-performance computing (HPC), i.e., user interactive, latency critical, and operations on large data sets split across a number of servers. This paper presents a power saving solution for datacenters that especially targets the distinctive characteristics of the scale-out applications. More specifically, we take into account correlation information of core utilization among virtual machines (VMs) in server consolidation to lower actual peak server utilization. Then, we utilize this reduction to achieve further power savings by aggressively-yet-safely lowering the server operating voltage and frequency level. We have validated the effectiveness of the proposed solution using 1) multiple clusters of real-life scale-out application workloads based web search and 2) utilization traces obtained from real datacenter setups. According to our experiments, the proposed solution provides up to 13.7% power savings with up to 15.6% improvement of Quality-of-Service (QoS) compared to existing correlation-aware VM allocation schemes for datacenters.

In this paper, we propose an event-driven black box surveillance camera which reduces energy consumption by waking up the system only when an event is detected and dynamically adjusting the video encoding and the resultant image distortion according to the criticality of captured frames called significance level. To achieve this goal, we find an encoding bitrate minimizing the energy consumption of the camera while satisfying the limited memory space constraint and distortion requirement at each significance level by judiciously allocating bit-rate to each significance level. To do that, we considered the trade-off relations between the total energy consumption vs. encoding bit-rate according to the significance level. For further energy savings, we also proposed a low complexity solution which adjusts the energy-minimal encoding bit-rate based on the dynamically changing event behavior, i.e., timing and duration of events. Experimental results show that the proposed method yields up to 67.49% (49.19% on average) energy savings compared to the conventional bitrate allocation methods.

Growing needs for surveillance in locations without power lines necessitates the development of a surveillance camera with extremely low-power consumption and an assured stable operation until the time of expected run-out of available energy. This paper proposes an algorithm for scheduling of video encoding configurations in a battery-operated surveillance system to reduce the image distortion while assuring the sustained operation until the battery recharge/exchange. The optimal video encoding configuration is determined based on the amount of estimated remaining event duration (considering the uncertainty of events) and remaining battery charge (considering the rate-capacity and recovery effect). The proposed algorithm consists of two steps: design-time step and run-time step. In the design-time step, prediction of remaining event duration, called duration prediction, is performed considering the uncertainty of events and tradeoff between encoding power and image quality. During run-time, video encoding configuration is switched between intra-frame encoding and inter-frame encoding based on the duration prediction obtained in design-time step and the remaining battery charge measured in run-time step. Compared to the conventional method based on the most conservative duration prediction , experimental results show that the proposed method provides 2.24~3.78 dB improvement in the image quality (in terms of peak signal-to-noise ratio in the H.264 encoding of four video sequences while satisfying the battery constraint.

In battery-operated wireless video surveillance systems (WVSS), it is mostly required to detect events in an energy-efficient manner due to limited available energy and a huge amount of data to be processed. Therefore, one of the main challenges in the battery-constrained systems is to minimize the energy consumption of the whole system. In this paper, we present an energy-aware event detector which has a hierarchical decision architecture to maximize the system lifetime while achieving the required detection accuracy. An analytical model for the relationship between the complexity of the event detector and system performance is derived based on the given event characteristics. Finally, we suggest a heuristic search algorithm to significantly reduce the heavy computational complexity. Experimental results have shown that the proposed heuristic search algorithm provides 98.17% complexity reduction on average with a negligible deterioration of the system lifetime.

We proposed a scheme to improve the lifetime of multi-camera system and the quality of its captured image by appropriate sharing of such resources among camera nodes as battery and memory based on low-power wireless communication links among camera nodes. The proposed scheme determines which camera node captures the event and which camera node stores the captured event by jointly considering residual battery charge, remaining memory space, wireless communication overhead, and the image quality captured by each camera node. Experimental result has shown that the proposed scheme achieves up to 4x lifetime extension as well as 43.19% improvement of the image quality (as measured by the face detection rate) compared to a conventional method [12].

3-D integration is a new technology that overcomes the limitations of 2-D integrated circuits, e.g., power and delay induced from long interconnect wires, by stacking multiple dies to increase logic integration density. However, chip-level power and peak temperature are the major performance limiters in 3-D multi-core architectures. In this paper, we propose a runtime power management method for both peak power and temperature-constrained 3-D multi-core systems in order to maximize the instruction throughput. The proposed method exploits dynamic temperature slack (defined as peak temperature constraint minus current temperature) and workload characteristics (e.g., instructions per cycle and memory-boundness) as well as thermal characteristics of 3-D stacking architectures. Compared with existing thermal-aware power management solutions for 3-D multi-core systems, our method yields up to 34.2% (average 18.5%) performance improvement in terms of instructions per second without significant additional energy consumption.

Most complex software programs are characterized by program phase behavior and runtime distribution. Dynamism of the two characteristics often makes the design-time workload prediction difficult and inefficient. Especially, memory stall time whose variation is significant in memory-bound applications has been mostly neglected or handled in a too simplistic manner in previous works. In this paper, we present a novel online dynamic voltage and frequency scaling (DVFS) method which takes into account both program phase behavior and runtime distribution of memory stall time, as well as computational workload. The online DVFS problem is addressed in two ways: intraphase workload prediction and program phase detection. The intraphase workload prediction is to predict the workload based on the runtime distribution of computational workload and memory stall time in the current program phase. The program phase detection is to identify to which program phase the current instant belongs and then to obtain the predicted workload corresponding to the detected program phase, which is used to set voltage and frequency during the program phase. The proposed method considers leakage power consumption as well as dynamic power consumption by a temperature-aware combined Vdd/Vbbscaling. Compared to a conventional method, experimental results show that the proposed method provides up to 34.6% and 17.3% energy reduction for two multimedia applications, MPEG4 and H.264 decoder, respectively.

Success of workload prediction, which is critical in achieving low energy consumption via dynamic voltage and frequency scaling (DVFS), depends on the accuracy of modeling the major sources of workload variation. Among them, memory stall time, whose variation is significant especially in case of memory-bound applications, has been mostly neglected or handled in too simplistic assumptions in previous works. In this paper, we present an analytical DVFS method which takes into account variations in both computation and memory stall cycles. The proposed method reduces leakage power consumption as well as switching power consumption through combined Vdd/Vbbscaling. Experimental results on MPEG4 and H.264 decoder have shown that, compared to previous methods and, our method achieves up to additional 30.0% and 15.8% energy reductions, respectively.

An event criticality-aware wireless surveillance system tries to minimize the energy consumption by adjusting the image distortion (or quality) requirement according to event criticality. In this paper, we present a novel video encoding method which scales bitrate so as to minimize the energy consumption of the wireless surveillance system while satisfying the given memory constraint. Given event statistics, memory size, and distortion requirement, the presented method gives an energy-optimal bitrate based on an analytic formulation of energy-rate-distortion (E-R-D) relationship for the target system consisting of H.264 video encoder, event detector, transceiver and memory. Experimental results show that the proposed method offers up to 59.6% (29.1% on average) energy savings compared to an existing bitrate allocation method which does not consider event statistics.

Crossbar switch network has an increasing impact on such critical measures as throughput, latency, area, and power consumption of complex system-on-chip as technology scales to deep submicrometer. With high clock frequency crossbar switch network design, global wire delay and pipeline registers inserted for throughput are important because they affect area, frequency, and power consumption of the chip. The traffic congestion is also a very important factor because it leads to the lowering of throughput of the crossbar switch network. In this paper, we present a topology synthesis method for the low-power cascaded crossbar switch network satisfying the given bandwidth, latency, frequency, and area constraints. Unlike previous papers, our paper considers wire delay, traffic congestion, and pipeline register insertion at the same time. Experimental results show that the topologies optimized for power consumption for a given clock frequency consume less power than existing methods by up to 38.04%.

At high-operating temperature, chip cooling is crucial due to the exponential temperature dependence of leakage current. However, traditional cooling methods, e.g., power/clock gating applied when a temperature threshold is reached, often cause excessive performance degradation. In this paper, we propose a method for delivering lower energy consumption by integrating the cooling and running in a temperature-aware manner without incurring performance penalty. In order to further reduce the energy consumption, we exploited the runtime distribution of each sub-segment of a task called “bin” in an analytical manner such that time budget for cooling in each bin is allocated in proportion to the probability of the occurrence of the bin. We apply the proposed method to two realistic software programs, H.264 decoder and ray tracing and a benchmark program, equake. The experimental results show that the proposed method yields additional 19.4%-27.2% reduction in energy consumption compared with existing methods.

Complex software programs are mostly characterized by phase behavior and runtime distributions. Due to the dynamism of the two characteristics, it is not efficient to make workload predictions during design-time. In our work, we present a novel online DVFS method that exploits both phase behavior and runtime distribution during runtime in combined Vdd/Vbb scaling. The presented method performs a bi-modal analysis of runtime distribution, and then a runtime distribution-aware workload prediction based on the analysis. In order to minimize the runtime overhead of the sophisticated workload prediction method, it performs table lookups to the pre-characterized data during runtime without compromising the quality of energy reduction. It also offers a new concept of program phase suitable for DVFS. Experiments show the effectiveness of the presented method in the case of H.264 decoder with two sets of long-term scenarios consisting of total 4655 frames. It offers 6.6% ∼ 33.5% reduction in energy consumption compared with existing offline and online solutions.

With a rapid increase of image resolution in recent mobile video systems, the memory bandwidth and power consumption have surfaced as critical problems in video coding. Despite many embedded compression algorithms proposed to overcome these problems, no proper algorithms have yet been reported with high enough throughput and no quality loss. This paper first proposes a lossless embedded compression algorithm with high compression ratio along with the hardware architecture for high throughput. Experimental results show that the proposed algorithm achieves at least 60% data compression without quality loss and bitrate increment. Moreover, the latency of the proposed architecture is sufficient to meet the real-time requirement of high-definition video coding, i.e., 30 cycles/macroblock. The proposed algorithm can be implemented with about 28 K gates.

This paper presents a method to customize instruction-set for configurable multiprocessors under a given silicon area budget so that total dynamic energy consumption is minimized when dynamic voltage and frequency scaling (DVFS) is employed. The proposed method is based on Mixed-Integer Linear Programming (MILP) to select the optimal processor configurations for real-time tasks from custom instruction candidates. We have evaluated the proposed method using real-life applications and commercial configurable processors. The results show that the optimally configured multiprocessors by our method has up to 23.2% reduction of dynamic energy consumption in comparison with the multiprocessors configured by a conventional approach.

Dynamic voltage and frequency scaling (DVFS) for a parallel software program is crucial for lowering the ever-increasing power consumption of multiprocessor systems-on-chips (SoCs). In this paper, we propose an analytical DVFS method that judiciously exploits slack by considering the varying parallelism over each path in a task graph. The proposed method overcomes the conventional pessimistic assumption on the remaining workload, i.e., worst-case execution cycle. It yields minimum average energy consumption by utilizing the runtime distribution of a software program while satisfying the deadline constraints. The proposed method tackles leakage power consumption as well as dynamic power consumption by combinedVdd/Vbbscaling. Compared to conventional method , experimental results show that the proposed method provides up to 49.20% energy reduction for a set of synthetic task graphs and yields 23.93% and 27.15% energy reductions for two multimedia applications, namely, the H.264 encoder and decoder, respectively.

Dynamic voltage scaling (DVS) is a very powerful technique in reducing dynamic power consumption of CMOS circuits. Recent studies showed that intra-task DVS method which adjusts the voltage level during program execution can achieve significant energy reduction. However, the overhead of large number of voltage switching becomes a limitation for its practical implementation. In this paper, we propose a novel task partitioning algorithm for intra-task DVS which partitions a given task so that the DVS can be applied more effectively with the minimum number of voltage switching. Experimental result using H.264 decoder software shows that the proposed algorithm reduces the energy consumption by up to 25% over the conventional method.

This paper addresses a problem of modeling the power consumption of advanced off-the-shelf processors. Unlike existing methods for processor power estimation, where the internal information of processor architecture such as activation of specfic modules such as pipeline stages, etc.) is available via simulation or runtime counters, power modeling method presented in this paper is to estimate the power consumption of complex off-the-shelf RISC processor without such a detailed information, only based on the information of the processor I/O signals (i.e memory access). To tackle this problem, we propose a new power model, called IPI(Instruction-Prefetch Interval) power model. The IPI represents the time interval between two consecutive instruction prefetchs. Our model has two major advantages. First, this model can consider prefetch mechanism. Most of advanced RISC processors have prefetch mechanism which makes processor power estimation difficult. IPI model is the first approach to model prefetch mechanism in processor power estimation. Second, this model can provide power variation in time and therefore it overcomes the limitation of previous work, such as instruction-level energy model. Experiments show that the proposed model yields 96% accuracy on theaverage in case of ARM1136JF-S test chip.

In this paper, we present the way of fast and accurate estimation of software energy consumption in off-the-shelf pro- cessor using IPI(Inter-Prefetch Interval) energy model. In our previous work[1], we proposed a new energy estimation method, and presented the way to characterize IPI energy model. However, there were some drawbacks in our previous work. First, the previous IPI energy model was only able to cover basic block. Second, it took too much time to estimate energy consumption of software due to the absence of energy estimator. To tackle these problems, in this paper, we propose modified IPI energy model, and present the way to implement IPI energy estimator using off-the-shelf system-level simulator. By using this, we can analyze such dynamic effect as address jump due to branch instructions and stalls due to hazard fast and accurately. The major challenging issue when implementing IPI energy estimator is cycle-by-cycle behavioral discrepancy between physical chip and ISS(Instruction Set Simulator) in system-level simulator. In order to overcome this problem, we propose training method to reduce the discrepancy. To verify our method, we applied our idea to ARM1136JF-S real chip. By the result of this work, the accuracy of energy estimation is more than 90% compared to measured data on prototyping board.