Emerging mobile services heavily utilize Neural Networks (NNs) to improve user experiences. Such NN-assisted services depend on fast NN execution for high responsiveness, demanding mobile devices to minimize the NN execution latency by efficiently utilizing their underlying hardware resources. To better utilize the resources, existing mobile NN frameworks either employ various CPU-friendly optimizations (e.g., vectorization, quantization) or exploit data parallelism using heterogeneous processors such as GPUs and DSPs. However, their performance is still bounded by the performance of the single target processor, so that realtime services such as voice-driven search often fail to react to user requests in time. It is obvious that this problem will become more serious with the introduction of more demanding NN-assisted services.

Continuous memory technology scaling causes memory cells to be vulnerable to wearout. To ensure reliable operations of circuits and systems in the presence of wearout, we require accurate estimation of the lifetime of circuits and systems degraded by wearout. Since the conventional method of estimating circuit and system reliability degradation based on device-level accelerated life test (ALT) does not account for the tolerance of a circuit and a system to a wearout failure of a device, accelerated lifetime testing at the circuit and system level is necessary. For accurate estimation of system reliability using system-level ALT, we propose a method that optimizes the design of experiments for ALT. From significant observations from failure data statistics of system-level ALT with various stress conditions applied to the memory system of the Leon3 as a case study, we define acceptability regions for memory testing of each wearout mechanism. In addition, by analyzing errors in estimating Weibull parameters from system-level ALT, we develop a methodology that optimizes experimental designs in acceptability regions of each wearout mechanism to minimize such estimation errors in system-level ALT.

We are experiencing an explosive growth in the number of consumer devices, including smartphones, tablets, web-based computers such as Chromebooks, and wearable devices. For this class of devices, energy efficiency is a first-class concern due to the limited battery capacity and thermal power budget. We find that data movement is a major contributor to the total system energy and execution time in consumer devices. The energy and performance costs of moving data between the memory system and the compute units are significantly higher than the costs of computation. As a result, addressing data movement is crucial for consumer devices. In this work, we comprehensively analyze the energy and performance impact of data movement for several widely-used Google consumer workloads: (1) the Chrome web browser; (2) TensorFlow Mobile, Google's machine learning framework; (3) video playback, and (4) video capture, both of which are used in many video services such as YouTube and Google Hangouts. We find that processing-in-memory (PIM) can significantly reduce data movement for all of these workloads, by performing part of the computation close to memory. Each workload contains simple primitives and functions that contribute to a significant amount of the overall data movement. We investigate whether these primitives and functions are feasible to implement using PIM, given the limited area and power constraints of consumer devices. Our analysis shows that offloading these primitives to PIM logic, consisting of either simple cores or specialized accelerators, eliminates a large amount of data movement, and significantly reduces total system energy (by an average of 55.4% across the workloads) and execution time (by an average of 54.2%).

Since memory cells tend to become more unreliable as technology scales down, to guarantee reliable operations of circuits/systems, prior to committing a design to manufacturing we need to accurately estimate the lifetime of a memory system by considering system usage. We propose to estimate the lifetime of a memory system using system-level accelerated life tests, where failures are detected with error-correcting codes. The difference from the standard approach to accelerated life tests of circuits/systems is that wearout simulation of circuits is used to select test conditions that are optimal for each wearout mechanism. In a case study, we investigate the reliability of a memory system in a microprocessor degraded by time-dependent dielectric breakdown, which is one of the major contributors to aging failures in modern computer systems. We estimate the probability of failure of the memory system at various stress conditions to define acceptability regions for TDDB for system-level accelerated life tests. The acceptability regions provide test conditions for each TDDB mechanism. We propose to use built-in self-test with fault detection via error-correcting codes during accelerated life tests, so that stress during accelerated test can track realistic usage patterns.

As dynamic random access memories (DRAMs) operate in the field, hard errors resulting from wearout occur. Unless corrected or repaired, hard errors halt normal operations, degrading the performance of a system and causing the replacement of memory modules. To improve performance and availability of memory modules, error-correcting codes (ECCs) are employed in a memory system. However, since recent field studies on DRAM errors have shown that a correctable error is highly likely to result in another error with the same address and in the same column or row, incorporating ECCs for mitigating not only soft errors but also hard errors in field operations is insufficient for ensuring reliable field operations. We propose a methodology that detects and repairs aging errors in DRAMs while operating in the field. We propose a methodology that reconfigures the remaining redundant resources after manufacturing-level repair into postpackage redundant resources. We also propose an ECC-assisted postpackage repair (PPR) flow that detects an error, identifies the type and location of the error, and invokes PPR for aging errors without built-in self-test/repair circuits. Employing a 2-GB ECC-dual in-line memory module of data-rate type three synchronous dynamic random access memories as a case study, we demonstrate that our PPR scheme improves the lifetime of DRAMs.

Because of continuous scaling down to small dimensions, DRAM has become a main memory with high capacity and density. Because denser memories are likely to contain more errors, DRAM employs repair schemes that replace errors with good cells for yield enhancement of a memory. The conventional repair scheme covers only manufacturing-level errors. As DRAM wears out while operating in the field, to enhance the lifetime of a memory, we need to incorporate a post-package repair scheme into a memory system for repairing aging errors. In this paper, we propose a methodology that repairs aging errors in a memory during field operations. Using the memory yield and lifetime simulator, we evaluate the proposed repair method. Employing a 2GB DDR3 ECC-DIMM as a case study, we demonstrate that our post-package repair scheme improves the yield and the lifetime of a memory.

We present an electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. First, the built-in self-test (BIST) system detects wearout and identifies the locations of the faulty cells. Next, the physical location of the failure sites within SRAM cells is determined. There are some fault sites for different mechanisms which result in exactly the same electrical failure signature. For these faulty sites, the cause of failure probabilities for each wearout mechanism is estimated by matching the observed failure rate from BIST and the failure rate distribution computed by simulation and as a function of circuit use scenarios. The estimation of wearout distributions is helpful in determining the wearout limiting mechanisms in the field.

Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention times of cells, and perform faster refresh only for a few rows which have cells with low retention times. Unfortunately, retention times of some cells can change at runtime due to Variable Retention Time (VRT), which makes it impractical to reliably deploy multirate refresh. Based on experimental data from 24 DRAM chips, we develop architecture-level models for analyzing the impact of VRT. We show that simply relying on ECC DIMMs to correct VRT failures is unusable as it causes a data error once every few months. We propose AVATAR, a VRT-aware multirate refresh scheme that adaptively changes the refresh rate for different rows at runtime based on current VRT failures. AVATAR provides a time to failure in the regime of several tens of years while reducing refresh operations by 62%-72%.

DRAM scaling has been the prime driver for increasing the capacity of main memory system over the past three decades. Unfortunately, scaling DRAM to smaller technology nodes has become challenging due to the inherent difficulty in designing smaller geometries, coupled with the problems of device variation and leakage. Future DRAM devices are likely to experience significantly high error-rates. Techniques that can tolerate errors efficiently can enable DRAM to scale to smaller technology nodes. However, existing techniques such as row/column sparing and ECC become prohibitive at high error-rates.