Serverless computing frameworks allow users to execute a small application (dedicated to a specific task) without handling operational issues such as server provisioning, resource management, and resource scaling for the increased load. Serverless computing originally emerged as a Cloud computing framework, but might be a perfect match for IoT data processing at the Edge. However, the existing serverless solutions, based on VMs and containers, are too heavy-weight (large memory footprint and high function invocation time) for operating efficiency and elastic scaling at the Edge. Moreover, many novel IoT applications require low-latency data processing and near real-time responses, which makes the current cloud-based serverless solutions unsuitable. Recently, WebAssembly (Wasm) has been proposed as an alternative method for running serverless applications at near-native speeds, while having a small memory footprint and optimized invocation time. In this paper, we discuss some existing serverless solutions, their design details, and unresolved performance challenges for an efficient serverless management at the Edge. We outline our serverless framework, called aWsm, based on the WebAssembly approach, and discuss the opportunities enabled by the aWsm design, including function profiling and SLO-driven performance management of users' functions. Finally, we present an initial assessment of aWsm performance featuring average startup time (12μs to 30μs) and an economical memory footprint (ranging from 10s to 100s of kB) for a subset of MiBench microbenchmarks used as functions.

On behalf of the Program, Organizing, and Steering Committees, we would like to extend a warm welcome to everyone attending the European Test Symposium 2017 (ETS'17). ETS has been established as one of the main international forums and the larger forum in Europe that brings together the test community to discuss emerging ideas, views, and trends in the area of electronic-based circuits and system testing. Topics of interest include, but are not limited to, design-for-test, dependability, security, failure analysis and diagnosis, on-line test, automated test hardware, validation and verification, fault simulation, fault tolerance, automatic test generation, etc.

Dynamic power management has become essential for low power designs and systems. Whether intentionally or unintentionally, these power reduction techniques and corresponding management schemes can impact the hardware reliability and system resiliency in one way or the other. In this paper, we first examine the resiliency issues related to dynamically power-managed designs. Then we demonstrate how reliability issues can be mitigated by changing the way we implement power management mechanisms all the way from circuit to system software. We will also demonstrate how different alternative power management mechanisms can be utilized to achieve system resiliency without sacrificing performance and power savings.

Traditionally, low power design has focused on hardware -- building lower power circuits, communication networks, and memories. As we move into the Internet of Things era, however, it's becoming clear that low power solutions must encompass hardware and software to deliver system-level optimization. While such solutions sound desirable and simple in theory, their practical implementation is complicated. This talk looks at some of the issues involved and explores promising avenues for future innovation.

As technology scales deep into nanometer era, power and energy have become major design constraints, especially for energy-harvested and similar ultra-low power systems, such as embedded processors, remote sensors and implantable devices for the Internet of Things (IoT). Aggressive supply voltage scaling is one of the most efficient ways of reducing power and energy for digital circuits. Near-threshold computing (NTC), in which the supply voltage is close to the threshold voltage of the transistor, can provide a very high energy efficiency (10X or higher) compared to the traditional super-threshold region at the cost of significant (>10X) increase in time to complete a task. However, NTC can come with some major challenges such as decreased functional margins in various circuit elements and greatly increased sensitivity to process variations. To ensure correct functionality in the field, testing of NTC circuits faces some serious challenges, and possibly requires a paradigm shift from conventional testing methods.

There has been a lot of interest recently in design-for-security, while at the same time research opportunities in conventional DFT are waning. Is DFS the new DFT, since many similar techniques can be applied, or is DFS something new, requiring new approaches to be successful, or is DFS merely a distraction? The panel will discuss the issues and give the audience the opportunity to decide.

Improvements in chip manufacturing technology, driven by high degree of integration due to small device sizes and additional complex functionalities enabled by heterogeneous integration, have propelled an astonishing growth of computing systems. While the pervasiveness of these systems enables emerging application domains, however, this trend is facing serious challenges, both at device and system levels. As the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and resiliency of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process, while other factors appear because of high frequencies and nanoscale features. This paper overviews the vision by some of the key industrial players regarding the emerging resiliency challenges faced at the extreme nanoscale technologies.

No Trouble Found (NTF) has been discussed for several years [1]. An NTF occurs when a device fails at the board/system level and that failure cannot be confirm by the component supplier. There are several explanations for why NTFs occur, including: device complexity; inability to create system level hardware/software transactions which uncover hard to find defects; different environments during testing (power, thermal, noise). More recently a new concept, No Fault Found (NFF), has emerged. A NFF represents a defect which cannot be detected by any known means so far. The premise is that at some point the defect will be exposed - most likely at a customer site when the device is in a system. Given that we looking for a defect that we know nothing about and are theoretically undetectable it will be interesting to see what the panel has to say about the nature of these defects and how we intend to find them.

Crossroads have always been challenging: they require a decision; in Egyptian and Greek mythology they were often guarded by two sphinxes trying to cheat the traveler with their riddles. The two sphinxes, the knight and the knave, the lady and the tiger, are just few instances of difficult puzzles that have kept logicians and mathematicians busy for the last 5,000 years. Today, you are walking down Moore's Law road when you come to a crossroads: one road brings you into the land of emerging technologies: 14, 10 and 7 nanometer, FDSOI, FinFET, 3D-IC,… beyond and below; the other road holds you into the land of established technologies: 28, 40, 65, and 90 nanometers, possibly even above, A&M/S, MEMS,… Choosing the right road is critical to lead your project and your company to success, but making the right decision is increasingly difficult, as it encompasses complex technical and economic considerations. However, unlike the mythological traveler, you won't run into the sphinxes but, rather, into some of our industry best experts; unlike the sphinxes, they will strive to provide you with honest advice about the “road conditions”, and you are allowed to ask multiple questions to them to figure out which road is the best for you.

Presents a collection of slides covering the following topics: mobile security background; trusted execution environment; ARM TrustZoneTM; side-channel attack; and authentication.

For many years, a key aspect of Design-for-Manufacturability (DFM) has been adjustment of polygons in standard cell layout. Similarly, radically restricted design rules and unidirectional layout have been proposed as DFM-friendly design styles with the ability to dramatically improve yield. This paper looks at the history of such approaches over the last few technology nodes and shows that as we approach 10nm and beyond, both of these techniques have essentially run their course as lithography restrictions and related effects increasingly dictate key aspects of standard cell layout. In their place, new approaches to manufacturability and yield are increasingly important.

The conventional guard band design approach increases the SRAM Wordline (WL) pulse duration to operate successfully in all the process, voltage and temperature (PVT) corners. This can significantly increase the dynamic energy. This work presents a digital circuit that is able to track and control the WL pulse duration of the SRAM memory across PVT variations, to minimize the dynamic energy while maintaining robust operations. The circuit is applied on a 78kbit SRAM. The results are compared to the worst case margin approach and show a maximum write energy savings of 45% and 49% relative to margining voltage/temperature (VT) and process variations, respectively.

FinFETs have recently overtaken bulk CMOS transistors as the device of choice for systems-on-chip. This paper provides some background on FinFETs together with their associated manufacturing processes and shows how they influence physical design of standard cells as well as place & route and timing closure for larger blocks.

As dynamic variability increases with CMOS scaling, it is essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Three sequential circuit elements are described: TIMBER flip-flop, dedicated TIMBER flip-flop, and TIMBER latch. The TIMBER flip-flop uses two master latches and one slave latch to mask timing errors by borrowing discrete units of time from successive pipeline stages. It can be simplified to a dedicated TIMBER flip-flop that uses only two latches for time-borrowing (TB) at the expense of the flexibility of configuration as a conventional master-slave flip-flop. The TIMBER latch masks timing errors through continuous time-borrowing from successive pipeline stages, and supports runtime configuration as a conventional master-slave flip-flop. The TIMBER latch's continuous time-borrowing capability provides better time-borrowing capabilities at lower hardware cost, but the TIMBER flip-flop's discrete time-borrowing capability preserves the edge triggering property of a flip-flop, thus blocking the propagation of glitches and spurious transitions. In addition to evaluating the overhead and tradeoffs of TIMBER-based error masking on an industrial processor, the three circuits were also prototyped on an FPGA and their timing error masking capability was validated using a two-stage pipeline test structure.

In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually incurs significant overhead. We observe that most existing slack monitoring methods focus exclusively on monitoring path endpoints, which is not cost efficient from power and area perspectives. In this paper, we first propose SlackProbe methodology, which inserts timing slack monitors like probes at a selected set of nets, including intermediate nets along critical paths. SlackProbe can be used to detect impending delay failures due to various reasons (process variations, ambient fluctuations, circuit aging, etc.) and can be used with various preventive actions (e.g., voltage/frequency scaling, clock stretching/time borrowing, etc.). Then we perform thorough analysis of the potential benefits and caveats of SlackProbe over conventional approaches in terms of number of monitors required, monitoring efficiency and observability, delay margin, and design perturbation. Experimental results on commercial processors show that with 5% extra timing margin, SlackProbe can reduce the number of monitors by 12-16X as compared to the number of monitors inserted at path ending pins. SlackProbe can also improve the monitoring efficiency by up to 1.9X and improve the monitoring observability by up to 32%, as compared to endpoint monitoring.

In safety related applications and in products with long lifetimes reliability is a must. Moreover, facing future technology nodes of integrated circuit device level reliability may decrease, i.e., counter-measures have to be taken to ensure product level reliability. But assessing the reliability of a large system is not a trivial task. This paper revisits the state-of-the-art in reliability evaluation starting from the physical device level, to the software system level, all the way up to the product level. Relevant standards and future trends are discussed.

Circuit reliability in the presence of variability is a major concern for SRAM designers. With the size of memory ever increasing, Monte Carlo simulations have become too time consuming for margining and yield evaluation. In addition, dynamic write-ability metrics have an advantage over static metrics because they take into account timing constraints. However, these metrics are much more expensive in terms of runtime. Statistical blockade is one method that reduces the number of simulations by filtering out non-tail samples, however the total number of simulations required still remains relatively large. In this paper, we present a method that uses sensitivity analysis to provide a total speedup of ∼112X compared with recursive statistical blockade with only a 3% average loss in accuracy. In addition, we show how this method can be used to calculate dynamic VMIN and to evaluate several write assist methods.

In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually incurs significant overhead. We observe that most existing slack monitoring methods exclusively focus on monitoring path ending registers, which is not cost efficient from power and area perspectives.

It is our privilege to welcome you to the 44th IEEE International Test Conference (ITC) sponsored by the IEEE Computer Society and the Philadelphia Section. We are pleased to once again return to the Disneyland Resort Hotel in Anaheim, California - a great venue for ITC, the world's premier conference in test.

Today, there are several trends that are making the reliability analysis of complex integrated circuits an important challenge in industry. As transistor geometries shrink, the number of physical failure mechanisms is increasing while at the same time the number of transistors per chip is still growing. The rollout of new services is pushing compute demands both in handheld devices and in the data center which is driving up complexity and the level of integration. People are becoming critically dependent on mobile services and expect high availability. Looking forward to the deployment of the Internet of Things (IoT) where processors and routers will be embedded in billions of end-points, we are only going to see an increased demand for reliable computing. In this session, we bring together three different industrial perspectives on reliability. The first looks at the end-points, the second looks at the servers and the last looks at the economic drivers for reliability and the demand for new EDA tools for reliability analysis. In the first talk, Rob Aitken from ARM will discuss the reliability challenges in mobile applications. As mobile systems continue to increase in size and complexity, and user requirements are also becoming more stringent, it is important for designers of mobile systems to be aware of reliability issues, and to adapt their methodologies accordingly. This talk discusses the issues involved, from latent defects, through soft errors, aging and wearout, and shows how to consider these as part of the design process, how to quantify their effects, and how to mitigate them through design changes. In the second presentation, Burcin Aktan from Intel is going to discuss the evolution of the reliability features that are found in server applications. With so many processing units packed in data centers the reliability requirements on an individual device is growing, especially with integrated memory controllers and very high bandwidth data pathways. What was an “add-on” to a device function, 10–15 years ago, now needs to be considered carefully with stringent budgets distributed to each functional block that contribute to overall error rates. This talk will focus on the evolution of reliability features in a number of server products leading into the current state and look at how today's designers are dealing with the challenges of gathering requirements, translating these to design implementation and delivering quality features to customers. Finally we will close with remarks on future directions and possible research areas. In the final presentation, Olivier Lauzeral from iROC Technologies will discuss the importance of methodologies for the reliability analysis of complex SoCs. There is an inherent cost to adding reliability features in a complex IC and designers need to be able to make informed decisions about how much hardware to allocate for mitigation (redundancy, error correction, repair). A prerequisite to make such choices is clearly defined targets and this requires an economic framework where the cost of failures is understood. Once the reliability targets for a system and individual devices are established, there is a need for EDA tools which allow designers to compute the failure rate and failure modes within the device. This analysis must include all failure mechanisms (radiation effects, lifetime effects, manufacturing detects) and take into account the relevant de-ratings between faults and observed errors. This new EDA infra-structure is key for designers to make effective trade-offs in order to arrive at a cost effective design.

Although it is an integral part of any manufactured chip and a crucial step to guarantee the required quality, VLSI Test technology seems to become less attractive/interesting for the research community. Funding bodies are minimizing their funding in the area, scientists are moving to other hot topics, industry is not seriously supporting academia in the field, etc.

We propose an adaptive WWL pulse width and voltage modulation architecture for low voltage bit-interleaved 8T SRAMs. The 8T bitcell offers improved read/write margins but suffers from write and half select concerns when bit-interleaved [1]. Also, low voltage operation leads to a long-tailed write time distribution, requiring large timing margins and limiting Vmin. To minimize timing margins and reduce Vmin, both WWL pulse width and voltage level are adaptively modulated by monitoring written values through the read path. In a 65nm CMOS prototype chip, Vmin is lowered from 700mV to 500mV using this technique, providing 2.55× leakage power reduction and 2.4× active power reduction.

There is a growing need to reduce device power to meet environmental, thermal, packaging, operating cost and other constraints in enterprise and carrier class applications. These pressures affect all levels of design targeted towards non-mobile applications: in the data center and its cloud, in the corporate enterprise - storage and WAN, in servers and embedded processing platforms, and in telecom wired transport and wireless backhaul networks.

Low voltage operation of SRAM arrays is critical in reducing the power consumption of embedded microprocessors. The minimum voltage of operation, Vmin, can be limited by any combination of write failure, read disturb failure, access failure and/or retention failure. Of these, the write failure is often observed as the major Vminlimiter in sub-50nm processes. In addition, the current generation transistors have high-k metal gate (HKMG) and these are prone to degradation due to higher level of electric field stress. The degradation increases Vmindue to increase in dynamic write failures and eventually, static write failures as the supply voltage decreases. We show that there exists a critical breakdown resistance (Rcrit) for a given supply voltage at which the SRAM write failure transitions from being dynamically limited to statically limited. For a 32nm low-power SRAM, the value of Rcritincreases by ~9X as the supply voltage reduces from 1V to 0.7V. Further, we show that the commonly used SRAM write-assist (WA) techniques do not lower Rcritand can only improve the write-ability when the breakdown resistance, Rsbd, is larger than Rcrit.

This paper discusses one of the key challenges of design-for-yield: namely, the difficulty in correlating observed behavior with modeled behavior. In order to achieve good parametric yield, the design process must account for a large number of sources of variability in the silicon, ranging from those inherent in the device and wire models themselves through approximations made in library modeling, extraction, tool algorithms and so on. The problem is further complicated by defects and systematic errors that can be present in early silicon but are expected to be fixed as part of the volume ramp. In addition, environmental factors such as temperature and power delivery must be understood, and variation in the measurement equipment must also be correctly accounted for. Examples are given for validating standard cell and memory based designs as well as a general methodology that can be used to enable chip bring-up.

Progressive gate oxide breakdown is emerging as one of the most important source of stability degradation in nanoscale SRAMs, especially at lower supply voltages. Low voltage operation of SRAM arrays is critical in reducing the power consumption of embedded microprocessors, thus necessitating the lowering of Vmin. However, the oxide breakdown undesirably increases Fmindue to increase in dynamic write failures and eventually static write failures as the supply voltage decreases. In this work, we describe an analytical model based on the Kohlrausch-William-Watts (KWW) function to predict the degradation in the WLcritas the oxide breakdown increases. The KWW model also accurately predicts the efficacy of the word-line boosting and Vdd lowering write-assist techniques in reducing WLcrit. Simulation results from an industrial low-power 32nm SRAM show that model is accurate to within 1% of SPICE across range of supply voltages and severity of oxide breakdown with orders of improvement in runtime.

Dynamic stability analysis for SRAM has been growing in importance with technology scaling. This paper analyzes dynamic writability for designing low voltage SRAM in nanoscale technologies. We propose a definition for dynamic write limited VMIN. To the best of our knowledge, this is the first definition of a VMINbased on dynamic stability. We show how this VMINis affected by the array capacity, the voltage scaling of the word-line pulse, the bitcell parasitics, and the number of cycles prior to the first read access. We observe that the array can be either dynamically or statically write limited depending on the aforementioned factors. Finally, we look at how voltage-bias based write assist techniques affect the dynamic write limited VMIN.

To ensure that an intellectual property (IP) block is validated ahead of its use in an 'unknown ' system-on-chip (SoC) context, an holistic view of the integration process must be taken. We will focus on the challenges faced in integrating and manufacturing advanced low-power processor based SoC systems, which have dramatically increased the complexity & state space for logical and electrical validation. We describe the process taken by IP providers, tool vendors and the foundry supply chain to enable first time logical, electrical and manufacturing closure. We discuss how feedback is used to improve component IP validation strategies and interoperability and integration testing. We also cover techniques such as the role of hardware/software emulation for configuration testing, the application of formal techniques and advanced electrical rules checking. In addition, we will examine the role waivers and automated design-in guidelines to enable the integrator to balance risk reduction and design turnaround time. Finally we discuss manufacturing tests and how to link these back to improve the metrics used for component and integration level testing.

Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on next generation solutions for variability, with the main emphasis on design and architecture solutions. Specifically, this panel will discuss:• Would new architectures mitigate variability in 22nm and beyond?• Could design regularity effectively mitigate variability?• What design techniques can be used to minimize variability 'on-the-fly'?• What new techniques can be used for memories, register arrays and flip-flops?

Read and write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. In this paper, we review the efficacy of four leading write-assist (WA) techniques and their behavior at lower supply voltages in commercial SRAMs from 65nm, 45nm and 32nm low power technology nodes. In particular, the word-line boosting and negative bit-line WA techniques seem most promising at lower voltages. These two techniques help reduce the value of WLcritby a factor of ~2.5X at 0.7V and also decrease the 3¿ spread by ~3.3X, thus significantly reducing the impact of process variations. These write-assist techniques also impact the dynamic read noise margin (DRNM) of half-selected cells during the write operation. The negative bit-line WA technique has virtually no impact on the DRNM but all other WA techniques degrade the DRNM by 10-15%. In conjunction with the benefit (decrease in WLcrit) and the negative impact (decrease in DRNM), overhead of implementation in terms of area and performance must be analyzed to choose the best write-assist technique for lowering the SRAM Vmin.

With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred to as time-dependent dielectric breakdown (TDDB), is emerging as one of the most important sources of performance degradation in nanoscale CMOS devices. This paper describes an accurate analytical model to predict the delay of combinational logic gates subject to TDDB. The analytical model can be seamlessly integrated into a static timing analysis tool to analyze TDDB effects in large combinational logic circuits across a range of supply voltages and severity of oxide breakdown. Simulation results for an early version of an industrial 32 nm library show that the model is accurate to within 3% of SPICE with orders of magnitude improvement in runtime.

Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Two sequential circuit elements-TIMBER flip-flop and TIMBER latch-that implement error masking based on time-borrowing are described. Both circuit elements are validated using corner-case circuit simulations, and the overhead and trade-offs of TIMBER-based error masking are evaluated on an industrial processor.

Static noise margin analysis using butterfly curves has traditionally played a leading role in the sizing and optimization of SRAM cell structures. Heightened variability and reduced supply voltages have resulted in increased attention being paid to new methods for characterizing dynamic robustness. In this work, a technique based on vector field analysis is presented for quickly extracting both static and dynamic stability characteristics of arbitrary SRAM topologies. It is shown that the traditional butterfly curve simulation for 6T cells is actually a special case of the proposed method. The proposed technique not only allows for standard SNM ¿smallest-square¿ measurements, but also enables tracing of the state-space separatrix, an operation critical for quantifying dynamic stability. It is established via importance sampling that cell characterization using a combination of both separatrix tracing and butterfly SNM measurements is significantly more correlated to cell failure rates then using SNM measurements alone. The presented technique is demonstrated to be thousands of times faster than the brute force transient approach and can be implemented with widely available, standard design tools.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (μeff), where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE.

We review adaptive design techniques with particular emphasis on error-tolerant techniques. We compare and contrast traditional adaptive approaches with error-tolerant techniques and analyze the margins eliminated by each of them. We discuss the applications of the latter to on-chip communication and signal-processing. Finally, we focus on a specific example of an error-tolerant technique for general-purpose computing called Razor.

Low voltage SRAMs are critical for power constrained designs. Currently, the choice of supply voltage in SRAMs is governed by bit cell read static noise margin, writability, data retention etc. However, in the nanometer technology nodes, the choice of supply voltage impacts the reliability of SRAMs as well. Two important reliability challenges for current and future generation SRAMs are gate oxide degradation and soft error susceptibility. The current generation transistors have ultra-thin gate oxides to improve the device performance and they are prone to breakdown due to higher level of electric field stress. In addition, the soft error susceptibility of SRAMs has significantly increased in the nanometer regime. In this work, we have quantified the impact of voltage scaling on the soft error susceptibility of gate oxide degraded SRAMs.We show that when gate oxide degradation is taken into account, there exists an optimal voltage (Vopt) at which the bit cell Qcrit is maximized. Further, we show that both Voptand Qcritmaxare a function of the level of oxide degradation. Finally, we investigate the impact of technology node scaling and analyze the trend of Voptand Qcritmax. As the technology node shrinks to sub-45nm, both Voptand Qcritmax decrease sharply, thus significantly decreasing the reliability of SRAMs.

This talk discusses one of the key challenges of post-silicon validation: namely, the difficulty inherent in correlating observed behavior with modeled behavior. Validation must account for a large number of sources of inherent variability in the silicon, ranging from those inherent in the device and wire models themselves through approximations made in library modeling, extraction, tool algorithms and so on. The problem is further complicated by defects and systematic errors that can be present in early silicon. In addition, environmental factors such as temperature and on-chip power supply must be understood, and lastly variation in the measurement equipment must also be correctly accounted for. Examples are given for validating standard cell and memory based designs as well as a general methodology that can be used to enable chip bring-up.

DFM has taken shape by virtue of manufacturers defining a series of "DFM activities", related to parametric and stochastic yield analysis and recommendations for design changes to improve yield. The picture is made more complex because the view from integrated device manufacturers, pure play foundries, and fabless semiconductor companies is not necessarily the same as they have different needs and constrains. This panel brings together DFM practitioners from each of these communities to discuss real experiences on the adoption level achieved so far as well as the impact in the manufactured products. The panel should be of interest of designers moving to advanced nodes (to learn from the experience of those that have "done it already") as well as those in the leading edge (such that they can compare experiences).

Start of the above-titled section of the conference proceedings record.

Moore’s law has been a foundation of modern electronics, sustained primarily by scaling. But can this continue despite the serious problems of litho, variability, device physics, and cost? This panel looks at several possibilities. Perhaps Moore’s law will muddle through, as it has so far, with a combination of tools, process, and design. But even if technically possible, Moore’s law is in practice driven by economics, and economics might turn against further scaling. Also, we’ve all seen how performance of single cores has topped out, despite scaling. Might this be a fundamental problem with planar technologies, prompting the need to go 3-D to get further performance increases? Or might CMOS itself give way to other technologies, allowing Moore’s law yet another respite? Compare and contrast for yourself these four very different visions of the future of your job, your industry, and your personal gadgets.

The document was not made available for publication as part of the conference proceedings.

Test catches defective parts. Traditional DFT makes test-related activities more cost effective. Debug and diagnosis discovers why a design or part did not work. Yield relates to how many good parts can be shipped thus how many dollars can be received. As one would expect, all these areas are related. The issue becomes: Can information from one operation be geared to better another? This panel specifically considers how test/DFT can aid in debug & diagnosis. The discussion is then extended to capture the impact on yield management in riskier contemporary and future processes. Over the past few decades, each of the above domains have gone through cycles of research, development, maturity and overhaul to adapt to changes in the process & product environment. In fact, because increasing degrees of uncertainty is introduced with modern nanometer processes, debug & diagnosis and yield management are becoming more recognized and valued portions of the product creation flow. To forward this, test and DFT functions are experiencing re-development. In building, executing and sustaining a competence, key issues include time & information. That is, the problem must be understood, solved in for the short term and solved for the long term. In addition, solution scope must be properly framed and, if possible, adaptable to unexpected changes in the process and tooling environments. It is well recognized that information availability and access are pillars of a debug/diagnosis solution. DFT structures, design automation tooling, test programs, ATE applications and physical failure analysis are means to a bulk of this data. The follow through is the assimilation of this data into a yield management and test quality system. As the topic is broad, panel of test experts will focus on practical experiences concerning the use of test, crafted DFT or test environments to facilitate debug and diagnosis. Precise developments in tying debug/diagnosis to yield management will also be discussed.

Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. "Surgeons" suggest a GDSII-centered approach, potentially invasive, while "family doctors" recommend a more pervasive approach, starting from RTL. As in real life, "surgery" and "medicine" represent two different schools of thought in the DFM/DFY arena. Both involve risks. This panel examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad cross-section of semiconductor industry. Although there is general agreement among the panelists that both approaches are necessary and that prevention is the best way to proceed, they also acknowledge that the surgery may be unavoidable in such "hazardous" conditions as state-of-the-art technologies. However, as always, "the devil is in the details", and the diverse approaches to DFM presented below should make this panel quite interesting. We are also counting on the feedback from the IC design community to assess if these approaches are sufficient and practical enough to deal with the "health hazards". We are looking forward to an exciting discussion that will challenge our esteemed panelists

The five papers in this special section focus on autonomous silicon validation and testing of microprocessors and microprocessor-based systems. The papers cover several important aspects of the technical area: from first silicon validation and debug to manufacturing and production testing, including both software-based and hardware-based techniques and design-for-test methods that range from pure functional instruction-based to structural scan-based tests. The scope of the papers extends from embedded uniprocessors to multicore microprocessors.

While transistors per square millimeter and on-chip clock keep scaling smoothly according to Moore’s Law, Vdd does not, nor does Vth. This leads to a dramatic increase in chip power density, and to a significant shift in the balance between dynamic and leakage power. In spite of the recent effort made by EDA vendors in delivering novel solutions that help mitigating the effects on power consumption of technology scaling, the question of whether EDA industry is taking the low-power matter seriously still remains. This session will provide an answer to this intriguing question, by first offering a short review of the state of-the-art in design technologies for dynamic and leakage power minimisation. The session will then continue with a public “trial”, in which OEMs, IDMs, IP and fabless semiconductor vendors will play the role of the public prosecutor, against defendant EDA industry. The court’s ruling will tell us about the future targets the EDA vendors will pursue in low-power design technologies.

Summary form only given. With ever-shrinking process technology, there is significant concern about the effects of process variability on design margins, yield, and performance. In addition, reliability is a major concern with new technology, not only through classic means such as latent defects and NBTI, but also by new issues brought on by variability, small feature sizes, and power-saving features such as dynamic supply voltage scaling. This paper shows how process scaling will affect reliability and how this interacts with ECC and redundancy features

Design for manufacturability (DFM) is becoming increasingly important as process geometries shrink. The system-on-chip business model requires high quality, high yielding IP. This paper shows how DFM and DFY are integrated as part of IP delivery, using a set of metrics to identify and fix yield limiters without compromising power, area or performance

As device geometries continue to shrink, single event upsets are becoming of concern to a wider spectrum of system designers. These "soft errors" can be a nuisance or catastrophic, depending on the application, but they must be understood and their effects budgeted for. Ultimately, experimental measurement is needed to quantify soft error rates, but after-the-fact measurement is too late to make changes. This paper shows a methodology that can be used to estimate the soft error properties of individual IP blocks by using a combination of critical charge calculations and experimental data.

Summary form only given, as follows. Successful product development is based on successful design flows and methodology. This session explores three key and often-overlooked aspects of these flows: integrating a working system-on-chip from a diverse set of IP, packaging and the silicon/PCB interface, and finally manufacturing test. Discovering the dependencies that exist among the decisions and objectives at each stage of the flow can drive global optimization. The speakers will discuss the tasks, decisions and objectives of their portion of the flow. These are compared for apparent and non-obvious optimization opportunities. The discussion continues in a panel format that invites the audience to further explore the topic. The following position papers give insight into the session presenters' views on these topics. The presenters are: Tarmo Ruotsalainen, Nokia Mobile Phones Ltd, Finland; Sanjay Dandia, Philips Assembly and Test Operation, USA; and Bill Eklow, Cisco Systems, USA.

This work describes a modular design of a wrapper enabling BIST/BISR for small memories operating as register files or FIFOs in high speed applications such as graphics and networking. The wrapper allows for at-speed test at low overhead and enables a simple repair scheme when millions of bits are used in such memories. The wrapper is intended to provide a standardized interface between memory and test controller, and thus work with any BIST controller, and communication between the two is minimized and at a reduced frequency.

The System-on-Chip (SoC) model has evolved as a method to help design productivity keep pace with the ever-increasing capabilities of silicon manufacturing. The SoC design style employs design reuse, and reuse allows IP to be shared among many designs and across companies. The combination of SoC and the fabless semiconductor model have resulted in the disaggregating of IC manufacturing, leading to the specialization model shown in Figure 1. Where all these functions historically existed only within vertically integrated companies, now horizontally specialized companies provide manufacturing capability and supply IP.

The use of a single pass/fail threshold for IDDQ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describes a method of using "current signatures" which uses only simple comparisons on the tester, and which automatically scales with process variations which give a wide range of background currents. Dynamic thresholds are used, based on the ratio of maximum to minimum current. Using a single IDDQ measurement for each die, upper and lower comparator values are set, against which IDDQ for each vector in the suite is compared. Production data is presented to verify the validity of the method.

Historically, it has been common to treat design for testability (DFT) independently of design for reliability (DFR) and design for yield (DFY). DFT is viewed as an add-on to the standard design process — something that happens in parallel with design, but off the main path. DFR is seldom considered at all during the design process, with the exception of ESD circuitry, another add-on late in chip development. DFY is vague and mysterious to all but those involved in the deepest levels of physical design, and even those individuals do not always recognize that the source of their design rules is DFY.

Trends in System Level Integration (SLI) are analyzed. Based on projections from the SIA roadmap and other sources, the impact of achievable reuse on design and manufacturing cost is projected. Similar analysis suggests that while test execution cost is currently equivalent to design expense in its effect on total production cost, it will dominate in the future. Core testability and its relationship with core 'firmness' is also examined. The implications of these trends on core providers and integrators, standards, tester manufacturers and CAD vendors are investigated.

The use of a single pass/fail threshold for I/sub DDQ/ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describes a method of using "current signatures" which uses only simple comparisons on the tester, and which automatically scales with process variations which give a wide range of background currents. Dynamic thresholds are used, based on the ratio of maximum to minimum current. Using a single I/sub DDQ/ measurement for each die, upper and lower comparator values are set, against which I/sub DDQ/ for each vector in the suite is compared. Production data is presented to verify the validity of the method.

Since its inception, the pseudo-stuck-at fault model has demonstrated its usefulness in generating IDDQ patterns, calculating coverage, and diagnosing defects. However, the model's definition has lacked rigor, which has resulted in multiple, incompatible, interpretations. This paper provides a complete definition for the model and demonstrates how variations will cause a loss of defect coverage. The covering relationship between the pseudo-stuck-at (PSA) model and leakage faults is proven for all combinational CMOS cells. This relationship is extended to show the effect that undetectable PSA faults have on leakage fault coverage. It is shown how to apply the model to sequential cells such as flip-flops and latches. The PSA model is also extended to cover both short and open faults in chip interconnect. A weighting function is introduced to tie the coverage more closely to process defect statistics. Finally, experimental results are given to show the effectiveness of the model on actual ASICs.

No abstract available.

There has been some recent interest in the subject of whether circuits should be tested with built-in self-test (BIST) or automated test equipment (ATE). As with many such debates, neither extreme is a viable position, and the true answer lies somewhere in the middle. BIST patterns have their place with scan patterns, I/sub DDQ/ patterns, etc. as part of a test program driven by ATE.

The SEMATECH "Test Methods Evaluation" study, Project Number S-121, is an experiment to determine the relative merits of several test methodologies often used by SEMATECH member companies and other IC manufacturers. Conclusions drawn from the experiment thus far have indicated that each test methodology uniquely detects defects. This experimentation and analysis would not have been possible outside a consortium setting such as SEMATECH. Its conclusions may affect other major segments of the industry, including ATE manufacturers, CAD vendors, and academia. This paper gives a brief overview of the experiment and summarizes its findings.

This paper describes an experiment in which various semiconductor test methodologies (stuck-fault, functional, delay and IDDq) are applied to an ASIC device. The goal of this project is to provide the data that will enable manufacturers to optimize their application of the various tests. This project was supported through SEMATECH (Project S-121, "Semiconductor Test Method Evaluation ").

In its most basic form, algorithmic fault diagnosis consists of using a fault model to predict the behavior of faulty circuits, comparing these predictions to the actual observed behavior of defective chips, and identifying the predicted behavior(s) which most closely match the observations. The goal of the process is to enable failure analysis by identifying promising locations for further study. The process is successful if the actual defect is contained in the list of possible locations, and if that list is sufficiently small to permit a failure analysis engineer to investigate them. In short, advances continue in both fault models and matching algorithms, which together continue to improve the effectiveness of algorithmic fault diagnosis, in spite of the fact that duplicating the exact behavior of defects remains elusive.

This paper investigates the relative effectiveness of scan-based AC tests, IDDQ tests and functional tests for the detection of defective chips, particularly those exhibiting delay faults. Data are presented from an experiment in which a production ASIC was tested with a number of scan and functional tests, together with IDDQ. Results show that all tests detect unique failures, indicating the presence of additional unmodelled faults. The effectiveness of the AC tests shows that targeting additional faults produces better quality than relying on peripheral coverage of existing tests.

A process is presented to validate fault models used in fault diagnosis. Known defects are inserted, using a focused ion beam (FIB), into production ICs and their behavior is compared to that predicted in fault simulation. The fault model is refined until it matches the observed defect behavior. The process is then repeated with known defects in unknown ("blind") locations, and necessary modifications to the model are again made. Finally, the model is used to diagnose chips with unknown defects. Experimental results on several chips demonstrate the value of the approach, which can be extended to test pattern generation and test quality estimation as well as fault diagnosis.

This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. The first part addresses the issue of non-uniform distribution of detected faults. It is shown that there is a large difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases. The second part deals with the use of weighted, rather than unweighted fault coverages and investigates the use of readily-available extracted capacitance information to produce a weighted fault coverage which is more useful for producing quality estimates, without having to perform a full defect analysis. Results show significant differences in weighted versus unweighted coverages, and also that these differences can be in either direction.

Iddq testing, where quiescent current is measured for a variety of states in static CMOS circuits, has emerged as a useful fault detection technique. In this paper it is shown that Iddq tests may be used for precise diagnosis of defects, using both inter and intra-gate shorts as fault models. The effects of these models are compared, using chips from a standard cell ASIC run. Of the 151 parts in the sample, diagnoses have been obtained from 135 of them. In many of these cases, the predicted defects are confined to a single standard cell.>

In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults.>

Recent predictions about the aliasing behavior of linear feedback shift registers used in signature analysis with pseudorandom testing are validated experimentally. It is shown that the independent error model accurately predicts aliasing in these signature registers when test sets are selected at random. In practice, however, a circuit's test set is fixed, and it is shown that adopting a more general asymmetric error model, of which the independent is a special case, yields more accurate aliasing information, especially in the dynamic or non-steady-state region of the aliasing profile. The only additional information needed to apply the asymmetric model to signature analysis is the fault-free sequence. Since this sequence is needed in any case to compute the fault-free signature, the model can reflect test set ordering at no extra cost.>

Recently there has been renewed interest in fault detection in static CMOS circuits through current monitoring (“Iddq testing”). It is shown that accurate defect (diagnosis miay be performed with a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis. ‘The associated hardware is sufficiently simple that on-board implementation is possible.

This paper discusses the use of stuck-at fault coverage as a means of determining quality levels. Data from a part tested with both functional and scan tests is analyzed and compared to three existing theories. It is shown that reasonable predictions of quality level are possible for the functional tests, but that scan tests produce significantly worse quality levels than predicted, Apparent clustering of defects resulted in very good quality levels for fault coverages less than 99%.

A diagnosis method is proposed which may be used to locate faults in circuits tested with random or pseudorandom test vectors. No intermediate signatures are involved, and the external hardware required is not complex. This proposed diagnosis scheme, called DAPPER, is applicable to multioutput combinational circuits. DAPPER classifies faults initially by their detection probability for coarse resolution, and secondly using their first failing pattern and a conventional signature for fine resolution. This method uses offline posttest simulation to isolate a single fault with only a fraction of the simulation that would ordinarily be required. Additionally, any failures within the test hardware itself may be diagnosed using the method.>

An effort is made to validate experimentally predictions on aliasing in signature analysis registers under the independent error model. From the experimental results it appears that the independent error model accurately predicts the probability of aliasing in signature registers. The authors also provide justification for the adoption of a more general asymmetric error model of which the former is a special case; the latter can be used at no extra cost. Among the potential benefits in using the asymmetric error model is the subdivision of faults into classes based on pD and pDbar, the conditional probability, respectively, of the fault-free bit being 1 and the faulty bit being 0 and vice versa, whereby faults in a given class have the same probability of aliasing. Under the independent error model fault classification is based on a single parameter p. Use of an asymmetric model hence provides a better resolution in terms of the classification of faults based on aliasing probability. Experimental results also indicate that considering the asymmetric nature of circuit outputs yields more useful information, especially in the dynamic region of the aliasing curve.>

A comprehensive design methodology which includes built-in self-test (BIST) cannot be achieved without performance measures of BIST techniques. Exact and asymptotic expressions are derived for the aliasing probability of randomized syndrome testing using the independent error model proposed by T.W. Williams et al. (IEEE Trans. Computer-Aided Design, vol.7, no.1, p.75-83, 1988). It is shown that randomized syndrome testing outperforms signature analysis for a substantial class of functions, and that existing methods can be used to transform the remaining functions during test mode.>