Since 1979 various papers and have been published on modeling the gate dielectric using Time Dependent Dielectric Breakdown (TDDB) testing. There are primarily 2 models used, the linear E field model and the 1/E field model. These are based on different failure kinetics and both predict vastly different lifetimes for the dielectric. As a result the majority of I.C. manufacturers used the 1/E model for reliability predictions.

Recent trends in the integration of process-, device-, and circuit-modeling tools and the current rapid emergence of Unix-based computing environments of networked workstations and computer engines makes possible user-friendly, task-based CAD systems for technology optimization, characterization, and cell design. The authors discuss these trends and identify opportunities to use technology CAD tools in the development of competitive technologies and products. It is shown that the ability to provide design centering and extreme-case analysis related to process variables has been a key to aggressive design of robust IC products. This capability results from efforts in the early to mid-1980's to establish integrated modeling systems such as MECCA, the application of general-purpose optimization capabilities such as WATOPT and CENTER, and recent advances in open and powerful computing environments (principally Unix-based distributed resources).>