CMOS at the 45 nm node is in production now, and if everything goes according to plan CMOS at the 15 nm node should be in production in fewer than ten years. However, every technology has its limits and CMOS is no exception. While there will be billions of CMOS devices on a chip, and "mobility engineering" will continue to enable ever faster CMOS devices, band-to-band tunneling will push up the standby currents and severely cap the speed of any transistor requiring low standby power dissipation. Nonetheless, the glass for continuing the rapid progress in silicon technology appears half full because system designers need a lot more than fast transistors. These needs include increasingly large memory capacity and increasingly large memory bandwidth, huge amounts of data storage especially storage that can be accessed at much larger bandwidth than traditional magnetic disk storage, system-on-chip (SoC) integration and volumetrically dense system-level packaging. And, of course, the power dissipation must be consistent with the thermal and power dissipation requirements of the systems. In this talk, the fundamentals that could limit the scaling of CMOS at or beyond the 15 nm node will be discussed, and the silicon opportunities for meeting the system needs of "besides faster CMOS transistors" will be described. The emphases will be on opportunities in memory technologies and in exploiting SOI CMOS as a SoC platform.

The development of bipolar technology in recent years is reviewed, and trends for future development are projected. The developments clearly point to three salient features of today's advanced bipolar transistors, namely i) self-aligned structure, ii) deeptrench isolation, and iii) polysilicon emitter contact. Both i) and ii) allow advanced bipolar devices to have much higher circuit density and lower power-delay product than without these features. The polysilicon emitter contact allows bipolar devices to be scaled down vertically without suffering from problems of insufficient current gain or low emitter-collector punchthrough voltage. It is clear that while progress will continue in scaling the familiar high-speed ECL logic and memory, the integration level of these very-high-speed chips is severely limited by the accompanied power dissipation. One seemingly promising and yet relatively unexplored direction is to increase the integration level by taking advantage of circuits with much lower power-delay product than ECL, such as NTL, TTL, CIVIL, and MTL to improve the functional throughput. The technology challenges as well as the potential of submicrometer bipolar technology are also discussed.