The increasing demand for high-performance wireless communication, due to emerging applications such as augmented reality, virtual reality, and Internet-of-Things (IoT), has highlighted the need for enhanced Peer-to-Peer (P2P) communication in Wi-Fi networks. P2P communication, often implemented through technologies like Wi-Fi Direct and Wi-Fi Aware, plays a crucial role in enabling seamless device-to-device interaction. This paper explores two significant enhancements for improving P2P communication: enhancing base-channel P2P through the optimization of TXOP sharing for P2P groups, and improving off-channel P2P through multi-AP coordination for channel advertisement. First, we examine the enhancement of base-channel P2P communication by introducing a refined transmission opportunity (TXOP) sharing mechanism, where an AP allocates portions of its TXOP to P2P devices within a group. This allocation ensures that devices can transmit data within a controlled, synchronized framework, thereby reducing contention and improving overall throughput. Furthermore, the proposed improvements enable devices to efficiently share resources based on group-level needs, supporting latency-sensitive applications such as real-time media streaming. Second, we address the challenges of off-channel P2P communication in OBSS (Overlapping Basic Service Set) environments, where interference from neighboring networks can severely affect performance. Through multi-AP coordination, APs can advertise recommended P2P channels that minimize overlap with infrastructure operations, thereby providing cleaner and more reliable channels for P2P communication. In addition, this coordination also facilitates faster setup and more efficient operation of P2P links.

Approximate timed co-simulation has been proposed as a fast solution for system modeling in early design steps. This co-simulation technique enables the simulation of systems at speeds close to functional execution, while considering timing effects. As a consequence, system performance estimations can be obtained early, enabling efficient design space exploration and system refinement. To achieve fast simulation speeds, first the SW code is pre-annotated with time information and then it is natively executed, performing what is called native-based co-simulation. To obtain sufficiently accurate performance estimations, the effect of the system components must be considered. Among them, processor caches are really important, as they have a strong impact on the overall system performance. However, no efficient techniques for cache modeling in native-based co-simulation have been proposed. Previous works considering caches apply slow cache models based on tag search, similar to ISS-based models. This solution slows down the simulation speed, greatly reducing the efficiency of native based co-simulations. In this paper, a high-level instruction cache model is proposed, along with the required instrumentation for native simulation. This model allows the designer to obtain cache hit/miss rate estimations with simulation speeds very close to native execution. Results present a speed-up of two orders of magnitude with respect to ISS and one order of magnitude regarding previous approaches in native simulation. Miss rate estimation error remains below 5%.

The increase of computational power in embedded systems has allowed integrating together hard real-time tasks and rich applications. Complex SW infrastructures containing both RTOS and GPOS are required to handle this complexity. To optimally map system functionality to the hard-RT SW domain, to the general purpose SW domain or to HW peripherals, early performance evaluations at the first steps of the design process are required. Approximate timed co-simulation has been proposed as a fast solution for system modeling at early design steps. This co-simulation technique allows simulating systems at speed close to functional execution, while considering timing effects. As a consequence, system performance estimations can be obtained early, allowing efficient design space exploration and system refinement. To achieve fast simulation speed, the SW code is pre-annotated with time information. The annotated code is then natively executed, performing what is called native-based co-simulation. Previous native-based simulation environments are not prepared to model multi-OS systems, so the performance evaluation of the different SW domains is not possible. This paper proposes a new embedded system modeling solution considering dual RTOS/GPOS systems. A real Linux-based infrastructure has been modeled an integrated into a state-of-the-art co-simulation environment. The resulting solution is capable of modeling and evaluating all HW and SW system components providing the designer with valuable information for early system optimization and design space exploration.

Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task due to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology tools for automatic hardware and software synthesis for adaptive architectures.